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Schematic picture & plots would be good (not a fan of text method :D). Just to check, is your pmos & nmos model definitions are correct? I don't see any difference except Vfbn.
How to configure cdsinit for enabling custom hotkey in Cadence Schematic for hiding terminal & instance labels? For example, to remove probed nets, I have
hiSetBindKey("Schematics" "0" "geDeleteAllProbe(getCurrentWindow() t)")
Yeah, that's correct.
Leakage will be in ON state also. To find it, you have to seperate ON current first. I don't know how to you do that.
Yes, when output is settled 100%, then you can capture leakage. But, 5tau is at infinite, right? So, still there will be a very low ON current.
For higher tech nodes => 130nm , Id equations will help. Calculations will match your simulation results. But for lower tech nodes, lambda effect is more. Simulations are based on higher order equations. So, first analyse the simulation results of single nmos/pmos circuits. Apply these learning...
Connect differential inputs with DC source, no ac signal. Add ac=1 at VDD source. Now you are injecting ac noise at VDD. Run AC analysis from 1 to say 1GHz. Plot opamp Vout. This will tell you how is the Vdd noise attenuation at the Vout. More the negative value, the better is PSRR. Hope this helps.
You have to consider drain to bulk leakage also. So, both nmos will have different IDB leakage. Measure bulk leakage by connecting dummy voltage source from bulk to gnd.
Drain to source leakage will be same for both nmos since they are in series. For this, connect dummy Vsource at 2nd nmos...
with inverter input=1, pmos drain current gives you the leakage current.
with inverter input=0, nmos drain current gives you the leakage current.
Seperate both mos inputs. Give pmos 1, nmos 0. Then measure nmos or pmos drain current. This is total leakage current.
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