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Recent content by findsriharsha

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    Need help in designing V2I converter

    Final note: this issue has been solved. I implemented a diff pair with source degeneration resistor to achieve the required transconductance.
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    How to measure switch cap circuit power?

    Hello, I want to measure the power consumption of charge pump (its a double dickson charge pump built using switch cap circuits). Can anyone suggest how to measure the power in any state? When I try to measure the current going through the supply, there are spikes that settle down within the...
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    steps to calculate nmos and pmos threshold voltage using Cadence- Virtuoso- ADE L

    I think you are looking at netlist instead of dc report. Do this: After running DC sims, in ADE-L window, goto Results->print->Model Parameters and then select any device on the schematic.. a pop-up window with all device parameters shows up.. in that look for vt.
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    steps to calculate nmos and pmos threshold voltage using Cadence- Virtuoso- ADE L

    Just run a DC simulation and search for vt value of the mos device you are interested in the dc report..
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    Opamp with out an external bias current source!

    I am designing an opamp for super low power application. I am not getting a fixed bias current (generated using bandgap) to bias up the amplifier. I am trying to use pmos mosfet stack in triode region (acts as resistor) to generate bias current internally. The problem with this current is it...
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    How to simulate the input-offset voltage ????

    I know this is an old thread, but would like to add few points for any novice designers: We need to run monte carlo sims across worst case PVT to get "RANDOM" input referred offset. For systematic offset (which is not random, but caused by bad design may be :roll: ), it will show up in typical...
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    NMOS drain does not connect with VDD, PMOS drain does not connect with GND,why?

    I work in an 8V SiGe BiCMOS process. We have VCC GND=0 and VEE! Probably you are a digital designer! :P
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    How to find output impedance of a circuit?

    Hi, can anyone tell me how to simulate the output impedance of a circuit using cadence? Please help! Thanks!
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    How to give a user defined wave in cadence virtuoso?

    Or you can import MATLAB data points file into cadence and create an instance of it...
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    How to calculate width of metal that is between a pad and a block

    Re: Analog layout: Solve You can use the EM check tool in cadence and find out what should be the width required to carry 100mA through M1 of length L..
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    ASSURA: LVS problem having 2 labels on the same net

    You can as "Run short locator" to ignore power buses I believe. I am not a layout guy, but I often use the tool to run RC extracted sims of my design. I normally specify GND VCC VP33 in the "Virtual Connect Net Names". - - - Updated - - - You can use "Run short locator" to ignore power buses I...
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    comparator design help

    you can use a preamplifier stage.. http://gaia.ecs.csus.edu/~pheedley/EEE232/8b_comp_Yin_OptEynde_Sansen_JSSC92.pdf
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    MOSFET Clamp Devices in opamp.

    Hi Zeker, I was talking about point-1 you mentioned above. Can you suggest an IEEE paper or a book where I can find more information regarding this. Thanks!
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    MOSFET Clamp Devices in opamp.

    Hi, I have seen mosfet clamps in many analog circuits. Can anyone tell me what is the use of this? Does it improve the circuit recovery time if a large voltage spike appears at the input of opamp? Thanks in advance!

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