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Leo, also the excess gain added by cascode in this case is reduced by 2^0.5, you gain some headroom for the transistor near power rail, to prevent it from entering triode region, then its rds will be enhanced.
So, it is very difficult to judge (by simulation) whether shorter or longer L is...
as to your fig, i give a new one, with root locus, openloop and closed loop
frequency response. i think whether it is stable depends on the phase margin
measured at 0 dB. So, i think your design could be stable.
hey fantaci, in your mag response, where is 0 dB in Y axis? Is it the X axis?
I think you d better point it out first. For the cross point of 0 dB and your response
will be your loop bandwidth.
I think that divdier will not affect the jitter to much, for it could be taken as a
stage of vco. Then, the total contribution to the jitter will be no more than one
stage's. See Weigandt's thesis.
For pfd, I know nothing.
For lpf, I think that you must take care of the ground noise coupled...
Hi ablue,
I think that the differential version of Yang's vco is Maneatis' vco. For Yang's
vco, the power suppy and substrate noise rejection will be good, I think, which
is demonstrated by Yang's paper. But, you can design one Yang and one Maneatis,
try the make comparisons.
Yang's vco could...
Hi, could you try Yang's structure then? It is a paper appears in JSSC, the first
author is H C Yang. This vco cell is single ended, but the common mode performance is believed superior.
fold cascode + bias
Hi, is your opamp single-ended? It seems that there are a
complex-pole-complex-zero-pair in your design. I dont think it will exist in
fully differential design. So, if you are single ended, please check with a
smaller load cascode transistor L, and to verify the...
In fact, I dont know how to get a system with RHP pole. But, for systems with
complex poles, there will be large ripple when settling. Then, you need to distinguish
between stationary and simutanous signal. For a step signal, any frequency is
present, then with complex pole, there will be...
Hi,
I think that you need not to match M6's source voltage to the others.
At the same time, the current matching between M6 and M2 should be
kept by the input PMOS transistors. If possible, use normal cascode,
or use large L in these PMOS. Then it could work.
You need only to match M1 and M2's...
sine wave added ring oscillator
I think so too. But remember to control the DC operating point so that
the comparator can work. Please see Maneatis' classic paper on PLL and DLL.
By the way, I dont think that this comparator could help the jitter performance.
This could be derived by...
Re: About the p-channel input stage? (question about martin'
1. I think that the equation SR=Veff1*wta implies that, for a given input stage
Veff, if you need larger wta, then you must increase the current, then the SR.
Just so so. But what will happen if you maitain the current Iss? then...
Re: About the p-channel input stage? (question about martin'
I am with Markie that the gm/Id only relates to the over-drive voltage. The only
disadvantage for P mos input stage is that the gate area should be larger, which
induce large input cap.
I think that ring oscillator like Maneatis' structure could do it. I have ever
designed and measured one, with no more than 10 ps rms jitter at 1 GHz.
Since the frequency is only 10 MHz now, the jitter could be better. But you
need to re-set the current for this cell, mine is a bit large.
There are plenty of files on this topice, for example,
docs from maxim, its application note:
**broken link removed**
eesof.tm.agilent.com/pdf/jitter_background.pdf
Best wishes!
fehler
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