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Recent content by fede76pc

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    Are there any 5G mobiles out?

    Re: 5g mobile I think that research is still focusing on defining 4G. Also LTE, that is still not yet a fully defined, is not consideret 4G (someone call it 3.9G)
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    Technology: AsGa, CMOS, bipolar

    Hi, first of all I do not understand well your question in particular if you want to know if MOS or bipolar transistor can be realized in Gallium Arsenide (GaAs) technology. However, GaAS is a compound III-V semiconductor with direct energy gap, high electron mobility, low hole mobility, low...
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    How to design and connect some CMOS gates

    Re: CMOS Gates Hi Mostafa, well, in order to connect different gates, the first thing you to check are the nise margins. In particular, each logic gate is characterized byfour different logic level: V_IL, V_IH, V_OH and V_OL. V_IL is the maximum input voltage identified as a '0'. V_IH is the...
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    Search for Simple & Free PCB layout editor

    Hi Everybody,. please don't be hurt by my stupid question. Where can I find a simple and even free PCB Layout editor? I'd like to start designing simple PCB and I don't won't to buy any professional CAD tool. I tried a free tool for Linux but when I compiled it on my RedHat 7.3 distribution an...
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    Help with Synplify Modular Design

    Hi Guys, I've got a little problem that I know someone (or maybe all) cen solve for me. I have a big VHDL design made of several blocks; it is possible to synthetize each of them independently and them put them together (I mean the previously single synthetized blocks) in the whole design...
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    How to decrease time slacks in Synplify Pro?

    I suggest you an icremental approach to synthesis... The first time try oversetting the clock frequency (e.g. 200 MHz) and get the estimeted clock frequency. Then do a new synthesis step with a new clock frequency near to the previously found (use a little bit higher frequency than the former...

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