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Hi all,
I have a question about using Verilog to instantiate a VHDL entity with generic parameter.
VHDL entity:
entity xxx is
generic(a,b : integer);
port(
...
I use two method to instantiate this VHDL entity in Verilog.
1)
genvar i,j;
generate
for(i=1; i < N; i=i+1) begin :
for...
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