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Recent content by fateme_ayat

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    design D flip flop with calculate basic timing of it,such as setup and hold time

    hi I'm very sorry.I try explain my problem better. I should design a pipelined adder . In order to obtain frequency of this adder I should know setup and hold time of registers that put between stages : [ Tclk >= (dmax - dmin) +ts +th +2tskew ] this is clock period of "mesochronous...
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    design D flip flop with calculate basic timing of it,such as setup and hold time

    hi yes, I know what is the basic timing's flip flop. but I want a transistor implementation of special flip flop that clearly be mentioned technology (ie 180 nm) and setup and hold time. I want write sub circuit D flip flop in hspice and use that as register between pipeline stages. and because...
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    design D flip flop with calculate basic timing of it,such as setup and hold time

    hi friends how can i design a D flip flop and calculate setup and hold time for it? Is there possible design d flip flop with PSSL family of logic ? thanks in advanced
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