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Recent content by fat_123

  1. F

    design CCII HSPICE

    but for flow of current, resistor and voltage should be applied.? can I do like this: RX X T 100ohm V1 T 0 ac 1 RZ Z 0 1K or simply apply current : Ix X 0 AC 1 at X terminal 1594800471 and putting VY Y 0 DC 0?
  2. F

    design CCII HSPICE

    if i want to find current gain, then what input should i apply at X,Y and Z PORT and for impedance RX, RY and RZ, how to find the impedance plot and how to connect input ? please guide me
  3. F

    design CCII HSPICE

    also how much load resistance or capacitance should be connected?
  4. F

    design CCII HSPICE

    yes, its current conveyor. I have seen falstad simulator but if I want to find out impedance at different ports then what type of input and analysis should be done? how to do this in HSPICE
  5. F

    design CCII HSPICE

    hi everyone, I want to simulate CCII circuit and find out its parameters like current gain, voltage gain, the impedance at X, Y and Z ports, bandwidth. I am facing difficulty in doing analysis and connecting inputs and how to find impedance and all. Can anyone please suggest to me about its...
  6. F

    Is this CMRR plot correct?

    okay thanks, one more question, if i have used vdd and vss like 1.8 and -1.8v then how can i find CMRR in HSPICE
  7. F

    Is this CMRR plot correct?

    Hi, could anyone tell me is this plot correct? this is CMRR plot of 2 stage opamp
  8. F

    UGBW not achieved in opamp

    from .op command current in M8 is 31.55u M8/M6= 3.9
  9. F

    UGBW not achieved in opamp

    Iref=7uA and m5 twice the size of m6 so m5 current will be 14uA and across differential amplifier 7uA how can i find second stage current?
  10. F

    UGBW not achieved in opamp

    from .op command M1 gm/id=18.5 m7 gm/id=17.84
  11. F

    UGBW not achieved in opamp

    that means there is some problem in my design i have taken gm/id of m1/m2 ==21.1 = (2*3.14*1.24pF*19MHz)/7uA gm7=1304 (2.2*gm1,2*CL/Cc)
  12. F

    UGBW not achieved in opamp

    no no i designed it for bsim 4 bulk CMOS 32nm technology
  13. F

    UGBW not achieved in opamp

    because of technology scaling, short channel effects occur in cmos which deteriotes the performance of the circuit. therefore we shift from cmos devices to other devices like finfet,tfet. isn't it?
  14. F

    UGBW not achieved in opamp

    i am gettin 11MHz so can i consider it fine?
  15. F

    ICMR of 2 stage opamp

    hi, attached image is the plot of ICMR(input common mode range) my ICMR of 2 stage opamp looks like this. my specification was 0.2V-0.5V is the plot correct?

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