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Recent content by Farid Shamani

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    Increment an array of integers in VHDL

    Hi friends, I am wondering if there is any other way rather than FOR loop too increment an array of integers by a certain amount. I mean if I have a array of (12, 1, 15, 40, ... , 3) in next iteration all the elements increase by , e.g., one (13, 2, 16, 41, ... , 4). Thank you Farid
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    Metafunction in Partial Reconfiguration

    I have a synthesizable DRAM block which is instantiated by a .hex file. Since i have used altera_mf library, it produces a compiler generated partition named SLD_HUB:AUTO_HUB during the compile time. When i intend to do partial reconfiguration, Quartus II shows me an error "Detected unsupported...
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    Related to Partial reconfiguration

    It depends on what you want to do. PR applies only for core blocks LABs (logic Array Blocks), on-chip RAMs, DSPs... For other periphery block such as transivers, PLLs and I/Os other methods like DR (Dynamic Reconfiguration).
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    dynamic partial reconfiguration

    As far as i know, Quartus II v12.0, 12.1 & 13.0 supports DPR.
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    [SOLVED] Fmax in quartus II- Direct form FIR filter

    Thank you dear Tricky, It made me more confident ;)
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    [SOLVED] Fmax in quartus II- Direct form FIR filter

    It might be a silly question, but i wonder if having a higher Fmax is an advantage regarding to timing analysis. For example is a 200 MHz Fmax better than 120 Mhz or it is proportional to other criteria. I have implemented the VHDL codes regarding to Direct-Form FIR filter in both pipeline and...
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    [SOLVED] VHDL- Fatal error happens while using variables !!!

    Thank you friends, It seems 2-D arrays are condemned to be assigned only in one process.
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    [SOLVED] VHDL- Fatal error happens while using variables !!!

    Hi guys, I have a code which can be written briefly as: ---------------- P1: FOR i IN 0 TO 10 GENERATE PROCESS (clk, reset) BEGIN IF clk'EVENT........ X(0,i) <= Y(2i) + Y(2i+1); ---- e.g, X(0,1) <= Y(0,2) + Y(0,3)...
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    [SOLVED] Assigning indexed INPUTs to indexed OUTPUTs in VHDL

    Thank you Kevin But what if i want to connect inputs number 15 to 0, to output number 15 to 31? I have to manipulate the vectors?!? and one more Q, do i have to declare all 256 inputs and 256 outputs in ENTITY part or i can assume a vector for them as well? I think i should assume it. :-)
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    [SOLVED] Assigning indexed INPUTs to indexed OUTPUTs in VHDL

    Dear Friends, I have number of inputs and outputs as: inp0 inp1 inp2 ... to inp255 and outputs: outp0 outp1 outp2 ... to outp255 I want to assign them together in a way other than assigning one by one, which will take 256 times of assignments (e.g. outp0 <= inp0; outp1 <= inp1; and...
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    [SOLVED] Butterfly interconnection between input and output in VHDL

    Ooohhhhh man it is working properly... I wish i could add you to my friend list. You really helped me. Thank you :)
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    [SOLVED] Butterfly interconnection between input and output in VHDL

    Thank you friend. However I am not good at functions, you gave me the clue to go for them.. :)
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    [SOLVED] Butterfly interconnection between input and output in VHDL

    Dear AXCDD, Thank you for your reply. Since i am not that much familiar with functions and procedures, Does it make any sense if the inputs and outputs bandwidth are 16 bits?
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    [SOLVED] Butterfly interconnection between input and output in VHDL

    Dear friends, I want to make interconnections between arbitrary number of inputs and outputs. The method that i am thinking is to use one array as inputs and another array as outputs. Then, by using an arbiter, connect the output ports to the desired input ones. This is the link to the picture...
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