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this code was implemented well on modelsim but how to do it on xilinx ise .... i maen the decimal point numbers handling ....
xa=ang+1.570796325;
asign = 1.0;
xa1 = xa;
if (xa1<0)
begin...
I have to display the output (divided) frequency on LCD .. to check whether i am getting 9600 hz or not, also please let me know on which pin i should take the output on FPGA as i dnt have the cable to connect with j3 header...
PLZ can u tell how to force a clock signal to clk in simulation in modelsim 5.7... there is no option of force here....how will i check the simulation results?
---------- Post added at 13:04 ---------- Previous post was at 12:57 ----------
@deni i have changed the lines and given clock signal...
this is the code for frequency divider but i am not getting the output wave for divided clock.....
also is there any rule or formula for dividing the frequency from 50mhz to some other value? like how many bits of counter to use ???
module clockdivider(clkdivout,reset,clk);
input reset,clk...
i am designing a project of home automation through sms.
i want to add additional function that when i give the sms to put on the electric kettle then after a particular time when its temperature reaches 90 centigrade then i get a message on mobile (t290i sony ericsson) to put off the kettle .
i...
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