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Re: LVDS transmitter
If A delivers a ''01010101" pattern, I think there can't be such big offset as B or C.
If A delivers prbs pattern, maybe there is offset like B or C.
There are some relationship with bit rate, loading, and corss point of A and Ab.
Now I'm doing pll chip test. How can I test the curve of settling of control voltage(output of the charge pump in CPPLL), if this point has a exterior pad?
During simulation, we can give this point an inatial condition, then we can get the settling curve of control voltage, any method for...
switched capacitor cadence
1:non-overlapping clocks can be generated by VPWL, also can be generated by sircuits
2: u can use ideal switch or NMOS or pMOS or Xgates depending on practical case u want
hi, you can use pmos as inputstage
if you want improve niose performance, let us know that your op's structrue
and your noise summary which i mean is noise contribution
Added after 9 minutes:
hi, you can use pmos as inputstage
if you want improve niose performance, let us know that your...
Re: 65 nm Process and VCO
what kind of ring cell do you use ?
and what is your process?
ah, pn below -100dbc/hz@1M is not difficult for 65 process
more power and select a good structure, and optimum pn
psrr vco
hi, i have a question that why do u make a assumption that supply noise frequency is around PLL BW ? I mean if wo don't consider the low pass function of pll
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