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Recent content by EUverNE

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    advantages of using FPGA in final digital designs

    Re: Why FPGA? Hi FvM, I think that future upgradings are focusing to some bug fixes and improvements and not at major functionality modifications. So why not to use a micro and a flash eeprom? It's upgradeable too. If we "upgrade" a design in such a manner that will alter the whole...
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    advantages of using FPGA in final digital designs

    Re: Why FPGA? Hi barath, Manufacturing an ASIC from scratch in low volumes, i agree, must has an elevated cost. But, is that all? What if we could implement our FPGA based design with already prefabricated ASICs from various vendors. Is it still more cost effective to use FPGAs ? Aren't there...
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    advantages of using FPGA in final digital designs

    Why FPGA? Hi guys, While I'm still learning digital design using FPGA a query is bothering my mind. Why do we need to use FPGA in our final designs? Ok, i know that FPGAs are perfect for prototyping purposes due to their flexibility in developing various complex combinational functions. But...
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    Verilog up-down counter. (help needed)

    up down counter At the time being I'm afraid that i don't know what is "constrain the design properly" and how to do it. :? Do you mean that i have to adjust some options of the synthesis tool to auto insert a slight delay in the path of a preselected signal? (up_down in our case) Currently...
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    Verilog up-down counter. (help needed)

    design up-counter to down-counter Hi dcreddy, I see your point. We have one signal with dual role at the same time and that confuses the synthesis tool and we need to time separate the two functions. However in my textbooks i remember stating that is a bad programing technique to use buffers...
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    Verilog up-down counter. (help needed)

    verilog model+6 counter Hi dcreddy, Looking at the generated schematic diagram it seems that OUT[0] is properly connected to where it should be and is identical as the other OUT bits paths. I notice that in the waveform results window, (see attachment) between OUT signal changes (e.g. 12->10)...
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    Verilog up-down counter. (help needed)

    verilog how to check if a signal just changed Oh' boy, here comes the pain again. :cry: Just downloaded the code into the fpga board and nothing worked as it should. It worked fine in the simulator but not even close in real world. Both push-buttons (PB) decreased the counter by 2 units...
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    Verilog up-down counter. (help needed)

    sample code for up-down counter application IT WORKS!!!! You hit the nail on the head! I had tried variants of the basic code to no avail. I don't even remember how many days have been passed reading & coding again and again. I feel relieved now! Thank you very much dcreddy1980. :D :D...
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    Verilog up-down counter. (help needed)

    up/down counter "...Add a real clock signal to the module and change the always sensitivity list into @(posedge clk or negedge reset)." Hi Devas, Thanks for your reply. I will correct the comma with "or" keyword but i have already tried adding a real clock, and i ended up with a design that...
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    Verilog up-down counter. (help needed)

    up down counter.v Hi all, I'm new in learning digital design for FPGA using Verilog HDL and encounter some difficulties trying to experiment designing a simple up_down counter. While compiling the design, Quartus v.9 web edition reports too many warnings regarding "combinatinal loops..." and...
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