Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by eternalXL

  1. E

    problem with test bench for a PS/2 port bidirectional tramsmit

    Yes. Last night I got rid of the transmit subsystem and the Wishbone connect level, just tested the mouse module with receive subsystem but there was still nothing showed up in the outputs of the mouse module (xm, ym, ...) Here is a picture showing how the whole project looks like now, following...
  2. E

    problem with test bench for a PS/2 port bidirectional tramsmit

    Sorry I'm not fully familiar with this existing codes from a book. Could I guess the problem is in the transmitter subsystem(ps2_tx)? If I need to test the receiving first, the tri_c and tri_d should all be 0 then the ps2d and ps2d can be seen as only inputs? but how to make the change in the...
  3. E

    problem with test bench for a PS/2 port bidirectional tramsmit

    Thanks again for suggesting me to change all the same lines with the same name, the RTL schematic looks better now. The receiving subsystem goes first then the transmitting system, and here are two timing diagrams for the two subsystems, that's the idea I got for my test bench. Yes it should...
  4. E

    problem with test bench for a PS/2 port bidirectional tramsmit

    Thanks a lot for your reply. Sorry the very first code with name "ZPUino_mouse_test" is not the test bench. It's the top level that connect the signals of the host_mouse_is (as you said) to the Wishbone. Here is my codes of the test bench: LIBRARY ieee; USE ieee.std_logic_1164.ALL; --...
  5. E

    problem with test bench for a PS/2 port bidirectional tramsmit

    Sorry I should have posted the Verilog codes of the PS/2 mouse also. zpuino_mouse_test is just a name, in this file, I connect the inputs(clk, rst); the outputs(xm, ym, btnm, mouse_done_tick) and the inouts(ps2c and ps2d) with wishbone signals. (After that I will insert the mouse module into a...
  6. E

    problem with test bench for a PS/2 port bidirectional tramsmit

    Yes, I'm trying to "act as a mouse" to give value on the ps2d and ps2c lines, to test if the outputs (xm, ym, btnm, m_done_tick) are really giving data to wb_dat_o. On the test bench, I can only act as the mouse device, but to make the whole system, there should also be data sent from the FPGA...
  7. E

    problem with test bench for a PS/2 port bidirectional tramsmit

    Hi I'm a student doing a project now and I run into some problems about testing two inout signals. I'm inserting a PS/2 mouse module with Wishbone, but before so I need to test if the signals can really be transferred. Here is my codes: PS/2 mouse is written in Verilog and I mixed Verilog and...
See more

Part and Inventory Search

Back
Top