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Hi Raymond
If your are not following the foundry ESD rules for the NMOS/PMOS switch devices then you should not count on these devices for shunting ESD current at all.
Actually without some silicide blocking you better completely prevent 'snapback' in the transistor - snapback in one finger...
Dear Zopeon
I do not know the details about the 3.3V analog ESD cells from Faraday but to me it seems dangerous to use the same cells for protection of the 1.8V core devices that are far more sensitive than the 3.3V devices.
You'd better ask for 1.8V specific ESD solutions in the specific...
Hi RC,
Thank you for your question.
It is true that in some cases the analog switch will be safe even without dedicated protection. However in my opinion it depends on the stress case, gate and bulk bias of the switch and also on the circuitry connected to bulk/gate. Moreover, it could be OK...
Hi Mpandejee
A substrate pump is used to ensure uniform triggering of the parasitic bipolar NPN inside NMOS devices.
For instance if you are using silicided (no foundry rules) output drivers then a substrate pump circuit can be used to ensure that all device fingers are conducting the ESD...
Re: ESD design
Hi Mikersia
HHI - High Holding Current. There are indeed different techniques to increase the holding current of the SCR. However, many of these techniques (e.g. breaking up the anode/cathode to insert well taps) are covered by patents.
This means that you will need to obtain...
Re: ESD design
Hi Tia_design
1. "HVNMOS/HVPMOS solves the problem": I meant that this solves the problem for the possible wrong connections: the circuit will not get damaged from the +/-16V connections: the drivers should be able to reliably sustain these applied voltages. But this does not...
Re: ESD design
Hi Tia_design
OK: 18V tolerant HVNMOS/HVPMOS solves the problem. Now you just need to define the ESD clamp to protect the HVNMOS.
Be sure to decouple the Nwell (PMOS driver) from the 3.3V Vdd line to disable the diode up intrinsic in the PMOS. Similarly you will need to...
Hi manjula
1. Boost bus: Principle is to be able to use a higher gate bias at the NMOS power clamp to enhance the current capabilities of this NMOS transistor. There is a landmark paper on this approach by the people (Michael Stockinger et al.) from Motorola (now Freescale): "Boosted and...
Re: ESD design
Hi Tia_design
You will need to work with local protection clamps between Pad and Vss and between Vdd and pad or like Mikersia explains a bi-directional clamp between pad and vss or bidirectional between pad and Vdd.
However, just like Mikersia I fear that a standard digital...
Hi Mengcy
When you are using a secondary protection concept you typically have 2 DIFFERENT stages. One primary current path is created for the majority of the ESD current. This typically consists of a diode + bus resistance + power clamp for an IO to VSS stress case. For IO pads far away from...
Hi Teddy
Thanks for replying and clarifying. You are right that it is more difficult to protect high speed pins (Gbps for USB 3.0, SATA, PCIexpress, HDMI) and RF IO's.
And you are right that it makes sense to reduce the specification.
However I have some concerns:
Many will agree that it is...
Dear miznick. Thank you for the interesting question.
dick_freebird is right: The required ESD protection actually depends on the end customer as well as on the manufacturing capabilities.
The end customer may want to increase the specification because of fears of ESD during actual use...
esd-diodesata
This is a forum item specifically targeted at on-chip ESD discussions.
If you are running into problems with ESD or are uncertain about the selected approach you can post it here. I ('ESDsolutions') and other EDAboard members will help you as much as possible, point you to the...
esd protection diodes on outputs
Without knowing the details (technology, robustness of the drivers, size of the drivers, ESD protection concept for the core, ESD requirement...) it is difficult to answer this querstion. The resistor is placed there for a reason so you can expect that simply...
esd picture
Hi zhonghan
According to this figure: -2kV (negative zap) is applied at pin 1 with pin 2 at ground.
According to the figure (green reference line) there was a forward diode from pin 1 to pin 2 and some element for the reverse stress case (power clamp, local clamp or diode up +...
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