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It's sure to use low-voltage devices in the design of BG because of good matching. But local regulator is needed for BG. To reduce the input offset voltage, it's better to use HV-LV mixed design design for the error amplifier.
Use the folded-cascode opamp with the n-channel differential pair transistors. This structure can extend the common mode input range beyond the power rail. I think it's difficult to get the speed target of 20ns with the quiescent current of 10uA.
If you use HSPICE to see the simulation result of the current in the circuit, you should set "method=gear" in ".options" to avoid the current oscillation.
The ft of the mos transistor is expressed approximately to the equation " ft=u*(vgs-vt)/2/pi/L^2". Therefore, short-length mos transistors have higher ft than long-length ones.
Please refer to the paper "A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at nyquist input, jssc,vol. 36 no. 12 Dec. 2001". A two-stage amplifer has been presented with 100-dB of open loop gain and 2-GHZ GBW by using the 0.35-um CMOS process.
new designer
Now you should have a suitable simulator, I recommend the software " active-hdl" which provides many sample codes and toturials. Please check "www.activehdl.com" for details.
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