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Recent content by ericjohnson

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    error correction circuit for 1.5bit/stage pipelined ADC

    Have you actually tried your search criteria? I couldn't find the specific info which talks about error correction circuit. If you know the link or a good reference, can you post it here? Thank you!
  2. E

    error correction circuit for 1.5bit/stage pipelined ADC

    1.5bit adc correction Can you please point me to the link or provide some schematic? I did search but couldn't find it at Berkeley's site. Thank you very much!
  3. E

    error correction circuit for 1.5bit/stage pipelined ADC

    1.5bit/stage Can someone please provide some good reference on how to design error correction circuit for 1.5b/stage pipelined ADC? If detailed circuit topology/schematic can be provided, that'll be greatly appreciated!
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    Getting 0% and 100% active PWM signal with 555

    pwm with 555 I think Sandra & Smith book is a good reference. -EJ
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    Info about finger layout of CMOS circuit

    finger multiplicity cmos Hi, fingering means to split wide transistors into smalll ones then connect them in parallel. This technique is usually used to get better matching between differential pairs. Hope this helps. Eric
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    Need free demo tool to learn the basics of synthesis

    Re: Synopsys newbie I believe many FPGA vendors such as Xilinx provide "demo" software which you could use to practice. Eric
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    How is it routing different from pre-routing ?

    Re: Routing and Pre-routing Never heard "pre-routing". Are you talking about placement or global routing before the detailed routing?
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    Whats the best circuit to delay clock? (CMOS)

    Re: How to make delay block? If I have a clock in, what is the best circuit to delay the clock according to the need? Thank you for your help. Eric Added after 29 seconds: BTW, this is for CMOS.
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    Cadence has acquired Verisity

    Cadence will be a lot stronger!
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    How to design an inverter buffer to drive a 1pF capacitance?

    Re: how to design a buffer? In theory, you can make an inverter chain with proper sizing to speed up the signal, if you know the loading capacitance. However, in reality, the calculated transistor size might be too large. So just use some approximation for the inverter chain sizing. Hope this...

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