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Recent content by erece

  1. E

    3.3 V to 1.8V level converter

    I want to convert a square wave with high level of 3.3 V & low level of 0V to a square wave of high level of 1.8 V and low level 0V. Frequency of square wave is 1 MHz in one case and 25 MHz in other case. I have the circuit for the converter as shown in the figure. I simulated this circuit both...
  2. E

    1.5 bit DAC (digital to analog converter)

    Does anyone know what 1.5 bit DAC is and why it is called so ?
  3. E

    delta sigma modulator implementation

    I am doing literature survey on delta sigma modulator. Pls suggest me some material on how to implement the modulator on hardware e.g i konw what the switched capacitor circuit looks like but do not know its working. Pls guide me.
  4. E

    discrete time delta sigma

    In CRFB structure of delta sigma modulator, what is 'resonator' here ?
  5. E

    is design engineer profile interesting

    i am an undergraduate student and undergoing internship in vlsi design. I am not getting any benefit from internship in terms of learning things in vlsi design. The only task i am assigned is to study the manual for ic design tool. All this i have to do on my own . Though the ic design tool is...
  6. E

    Top topics for electronics training

    I am doing engineering in electronics and communication. I want to do a 6 week training in 7th semester. Please tell some topics which companies look for .
  7. E

    Bandwidth efficiency in m - ary psk

    In M-ary psk Rb=Rs*log M log with base 2 Rb- bit rate Rs - symbol rate then bandwidth required for passband signal is B=Rs and bandwidth effeciency = Rb/B=log M log with base 2. Is the above formula for bandwidth efficiency correct ...
  8. E

    pn code synchronization

    In the frequency hopping acquisition ( which is the first step of pn code synchronization ) system why do we add time delays to each matched filter??
  9. E

    nyquist bandwidth criterion

    According to Nyquist bandwidth constraint for transmission without ISI , the minimum channel bandwidth should be R/2 symbols /sec, where R symbols /sec is the transmisson rate. If this is correct then i want to know that if this channel cannot support full transmission rate then do we use this...
  10. E

    [SOLVED] How many transistors do I need to design a CMOS XOR gate and 2:1 multiplexer?

    I am designing cmos logic xor gate and 2:1 multiplexer. In my design i am using 8 pmos and 8 nmos for 2:1 mux and 6 pmos and 6 nmos for xor gate. I am using pmos and nmos to implement complement A, means that i am not using complement directly into the circuit. So , i want to know that is it the...
  11. E

    vulnerable period slotted - ALOHA

    Why vulnerable period in slotted aloha is T and not 2T ?
  12. E

    current and voltage distribuition in the circuit

    thank you to both of you... My concepts are weak. i.e why it took me a lot of time..
  13. E

    current and voltage distribuition in the circuit

    I think you didn't take voltage drop from collector to base of Q2 in the last line to calculate voltage across 330 ohms resistor. Why so?
  14. E

    current and voltage distribuition in the circuit

    thanks for the reply............ I want to know the impact of base voltage of Q2 on Q2 and Q1. It is like base voltage of Q2 is the input voltage to the circuit... And you wrote that when Q1 is off Ie of Q2 will be 8.5 mA , but why did you take resistor 160 ohms. With Q1 off , no current will...
  15. E

    current and voltage distribuition in the circuit

    In the given figure , when base voltage of Q2 is made 3.2 V then why Q1 reaches cut off and Q1 in active region and when base voltage of Q2 is made 3.5 V the why Q2 reaches active region and Q1 in cut off ??

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