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Recent content by eramardeepsingh

  1. E

    VLSI DSP tutorials or online study material

    Hello friends I need help regarding some topics in m.tech. vlsi design syllabus for ppt preparation Introduction to DSP ASIC Design Configurable Logic for Digital Signal Processing Design Methodology for DSP VLSI Implementation of DSP Processors please help me. I need tutorials...
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    Help about designing of FPGA's

    Thanks to all of you friends for providing valuable information about FPGA designing
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    Help about designing of FPGA's

    Dear all friends Please anybody suggest me in which software the designing of FPGA's can be done. I can design USART on FPGA, Multiplexed display controller on FPGA, CRT controller on FPGA. Please help me to suggest proper software to do all the lab work
  4. E

    Tutorials to run cmos design on orcad pspice software

    Dear all users I need help regarding how to design CMOS Inverter or nmos inverter or other designs in the orcad pspice software. Can any body provide steps to design cmos inverter. Kindly help i am not known about this software.
  5. E

    Kindly anyone provide these books links

    Respected All Users I need two books for my M.Tech. VLSI Design studies Physics of Semiconductor Devices by S M Sze 3rd Edition Analog VLSI signal and Information processing by Mohammed Ismail I require these books urgently. Kindly anyone helps me to find out these books
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    2 bit counter as finite state machine

    sir what is problem in second program as and what are input parameter for both i am confused about that library ieee; use ieee.std_logic_1164.all; entity mealy_4s is port ( clk : in std_logic; data_in : in std_logic; reset : in std_logic; data_out : out std_logic_vector(1 downto 0) ); end...
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    2 bit counter as finite state machine

    Sir I have trying for coding of 2 bit updown counter as finite state machine. Now there is problem in my coding, and i am also confused about the input parameter to be used in this case. I have using active hdl software for coding of counter. Finally i wants the simulation waveforms. I am...
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    2 bit counter as finite state machine

    Sir the link provided by you gives some error and sir i am beginner in this field so please tell me steps in active hdl software. is the type state_type is (s0,s1,s2,s3); and signal current_s,next_s: state_type; is declared in where the inputs and outputs are declared. Please help i will...
  9. E

    2 bit counter as finite state machine

    Please any one can provide the code of 2 bit counter as finite state machine in Active HDL. Please help me.
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