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Hi experts,
We choose this ADM1278 hot-swap controller. I use HotSwapDesigner to calculate Rsense 0.3mohm for 293 A threshold. Would you advise what the timing can handle if a system could run surge current 253A , 200us. I read the datasheet, but don't which it's the timing.
1. Should I refer...
Hi experts,
Since there is a design error, we didn't add a pull-high resistor to an input pin. It's floating now and caused malfunction sometimes (the status should be active low). Are there any suggestions for quick rework on PCB? wire to another pull-high resistor? Many thanks!
Hi experts,
There are several PCIe clock generators such as common clock, SRNS, and SRIS. It seems SRIS is for most designs, and some design is with SRNS. SRNS should be lesser noise? What are the pros and cons, and applications for PCIe Gen4?
Hi experts,
I study a SAS 9305 HBA card through a backplane to SATA HDD, how to design the backplane?
The left side is miniSAS HD and the right side is SATA.
I checked the pinout SAS and SATA is the opposite. Since 9305 HBA is SAS controller, should I follow SAS pinout? or stick to SATA...
One more question: The S2/S3 of U.2 SFF-8693 are different from SAS SFF-8482. So which link is right? The SATA0_TX from SFF-8643 cable should connect to S2/S3 or S5/S6 on backplane?
Basically, the signal should be TX -> RX from 4 * mini-SAS HD to 16 * SATA connector, but there is a wrong pinout on the backplane. The link is TX -> TX and RX -> RX now. What will happen in this case such as malfunction, can't receive any data, etc.? Is there any automatic reverse mechanism...
Hi experts,
As far as I know, the major difference is the data rate. The data rate of SPI is 10-20Mbps, QSPI is four times to 80Mbps, but the clock frequency of them are the same 25Mhz. QSPI doesn't require CPU intervention.
If I change a flash from SPI to QSPI, what else should I take care of...
Hi experts,
I study an NMI (Non-maskable Interrupts) function, but I don't know how it works detailedly. Please advise me on how and what the nets BMC_CPU0_NMI_CTL_N (BMC to CPU)、CPU0_BMC_NMI_ACTIVE_N (CPU to BMC) mean below.
I assume a server system crashes. Then, press NMI button. BMC sends...
Totally agree. Should modify the pull-up resistors first after study the **broken link removed**. Besides, there are only two chips (the resistors could cover 400pF). It shouldn't need the repeaters.
Thanks for your detailed explanation. The repeaters are not enabled indeed, so I thought it's not necessary too.
There are 2.2K pull-up resistors. I didn't attach it. Thanks for mentioning.
Hi Stenzer,
Thanks for your reply. All I2C is on a single PCB without cable and connector. The total length is around 21 inches, and the frequency is 1Mhz. It's a good point that is related to capacitances. So, what's the frequency or length that have capacitances generally?
1596604394
Hi FvM...
Hi,
I study the I2C divides into two nets with a repeater PCA9617ADPJ below (BMC_I2C3_SCL -> BMC_I2C3_OUT_SCL). Every kind of I2C is the same. It looks it's only for buffering (rise/fall time, not voltage shifting). Is it really needed?
Repeater datasheet...
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