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Hi,
I have a simple question, is there any restriction by technology vendors or fabrics on the size of Ram integrated on an ASIC chip? I mean can they be as big as the one want?
Cheers
Hi,
I am designing an intensive control algorithm in FPGA. The problem my design have a very good results more than good enough. How can I tradeoff the throughput to area if my design is a big statemachine (170 state minimum)?. Now if it was a datapath like a DCT,FFT etc one could suggest...
Hi,
I want to compare a couple of architectures implemented in different technology process eg 0.13, 0.18 and 0.25 um. Is the gate count a process independent metric?
For example one design was implemented in 0.13um used 32K gate and another was implemented in 0.18 um used 27k Gate, is it...
Thanks for the reply, actually 50 is the number of paths violating the setup time. But I am still confused so if they are false paths how come the simulation doesn't work with 5 ns clock.
Hi,
My design is working perfectly good after the post-synthesis (using DC) at clock rate of 5 ns.
In place and route(using encounter), I got 50 setup violating path. I tried to simulate the netlist and it worked but with a clock of 40 ns (might be not the corner but it didn't work with 5 ns...
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