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Recent content by energeticdin

  1. E

    What is Metal slotting? I need defintion and merits and deme

    Metal slotting Hi All What is Metal slotting? I need defintion and merits and demerits? Din
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    Which of those will not affect the function of chip in the long run?

    Hi , 1. Which will not affect the function of chip in longrun? a. Anternna DRC Vio b. Xalk glitch c. EM d. ALL Thanks
  3. E

    Reg: Primetime reading library

    Hi Please let me know whethr Primetime can able to read Lib .? Dinesh
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    Reg" set_clock_latency

    set_clock_latency Hi All, Please let me know, what is the value we have to given in general, set_clock_latency: I came to know that 30% of clock period for input delay and output delay For setup uncertainty 10% of clock period? Plz let me know this is rite? and how much we have to give...
  5. E

    Synthesis report doubts - the flip flop gate count

    Re: Synthesis report doubts Hi All, One More query, IF we are constraining area in Synthesis tool, i.e set max area 0 Then what tool will do? Whether tool put more effort to optimize area or increase run time? What about tool effort? Dinesh
  6. E

    Synthesis report doubts - the flip flop gate count

    Re: Synthesis report doubts Thanks a lot dcreddy1980 and jeniston Dinesh
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    Synthesis report doubts - the flip flop gate count

    Synthesis report doubts Hi, Please clarify, 1. From the following synthesis area report, how can we find out the flip flop gate count . Eg: Number of ports: 601 Number of nets: 1387 Number of cells: 92 Number of references: 17 Combinational area: 85900.859375 Noncombinational area...
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    Questions about ECOs and analyzing the timing reports in STA

    Re: Reg: STA Hi Sunil, I tried in Goldtime. I uploaded netlist and SPEF. After update_timing, Source eco_fix_violations.tcl But its giving some warning. I tried ur way of explanation. Plz let me know. Din
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    Questions about ECOs and analyzing the timing reports in STA

    Re: Reg: STA Hi Sunil, Thanks. Where will be eco_fix_violations.tcl available in PT. Din
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    Questions about ECOs and analyzing the timing reports in STA

    Re: Reg: STA Thanks a lot kssai Suggest some books to learn and analyze timing reports deeply. Thanks Din
  11. E

    Questions about ECOs and analyzing the timing reports in STA

    sdc file multimode Thanks kssai, Is ther any ECO flow? What is Multi mode/Multi-vt designs and timing closure? Plz tell me about this concept? Din
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    Questions about ECOs and analyzing the timing reports in STA

    Hi all, I come across one question? 1. In STA, if we find some of the cells which i need to upsize? After upsizing the cells, if the timing get even worse? What may be the reason? 2. While upsizing the cells, what are the things we need to take care? whether we have to see previous cell...
  13. E

    Verilog HDL Synthesis

    HI Anybody is having Verilog HDL Synthesis by J.Bhasker Please upload here or Send me mail energeticdin@yahoo.co.in Thanks in advance Din
  14. E

    Reg: Onsite VLSI jobs

    Hi , How to apply for Jobs in US, Korea, Japan ? Is ther any Link to apply? or only thro consultancy Thanks Din
  15. E

    set_max_capacitance and set_load

    set_load -wire_load HI Thanks. for eg: set_load 0.5 OUT1 On what basis, 0.5 pf constraints is loaded in SDC? How we will come to know this value? U r telling that set_load sets the capacitance to sp value on specified ports & nets and set_max_cap sets the max_captacitance to sp...
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