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Recent content by emont89

  1. E

    Transient noise analysis problem

    I have tried to look into this tab, but I have only found "gmin" but not "cmin"
  2. E

    Transient noise analysis problem

    Hello, I have tried to perform a transient noise analysis, but I received this error: ERROR (SPECTRE-16192): No convergence achieved with the minimum time step specified. I have read the possible solutions, but I don't know how to change "cmin". Do you have any suggestion? Are there other...
  3. E

    2-fingers CMOS transistors in Virtuoso

    Hello I have a question about fingering. If I create a 2-finger transistor, it is possible to create it with the D-S-D configuration or only with the S-D-S configuration_ In the case it is possible, which is the option in Virtuoso to set it?
  4. E

    Post-Layout noise analysis

    Hello, I have a question about post-layout noise analysis. When I select the noise analysis in ADE L it is required to choose a positive and a negative output node. In case of post-layout simulations, these node have to be choosen from the av_extracted view? Thanks!
  5. E

    Assura QRC capacitor coupling mode

    OK! Thanks a lot, now it is more clear!
  6. E

    Assura QRC capacitor coupling mode

    Ok, thank you for the reply! So the Coupled option is the most complete one, if the database is not too big this is the most correct choice I suppose.
  7. E

    Assura QRC capacitor coupling mode

    Hi all, I have a question about the Extraction tab of the Assura QRC editor. In the section "cap coupling mode" it is possible to switch between Coupled, Decoupled or Decoupled to Substrate . Which is the difference between these options and, above all, in which kind of parasitic simulation it...
  8. E

    Device noise simulation

    Ok! Thanks for this answer. I have a further question. If I type VN() or VN2() as output variable I can see the total output noise of the circuit. There is a way for seeing not the total noise but only the noise of a single device creating an output variable (not using the noise summary for...
  9. E

    Device noise simulation

    I'm using cadence virtuoso
  10. E

    Device noise simulation

    I'm simulating the noise of a circuit, but I want to use as an output variable not all the noise (represented by the VN2() function) but only the noise caused by a device (in this case the input transistor). Which method should I use?
  11. E

    Question about a DAC in veriloga

    I've created a DAC using veriloga(the code is below). My question is which function can I use in veriloga (in digital verilog the function posedge is used) to save the V(out) value only at the rising edge of the control signal? module DAC_verilog(ctrl,b0,b1,b2,b3,b4,out); input...
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