Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
hi all. i am working on developing 100G Ethernet PCS based on IEEE std.802.3bj-2014.
i am confused about the scrambler and 256B/257B transoder.
the tx flow described in IEEE 802.3bj-2010 standard is below:
Encode -> Scramble -> Block Distribution -> Alignment Insertion
-> Lane block sync ->...
the WDATA is not interleaving so the order of WDATA is the SAME witn the order of AW. Get the WDATA and AW together from the outstanding queue. when the WID is present in the old AXI version, a WDATA re-order mechanism will be inferred, and thanks to the remove of WID, we do not need that...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.