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Thanks a ton. I'll look those links up and get back..
---------- Post added at 05:49 ---------- Previous post was at 05:22 ----------
i'm not quite able to guage the number of temporary variable buffers needed to store the data in each line and store the five output values. which functions...
Hi all,
I have a perfectly working test bench code. This is the code i've written :
ENTITY final_packet_format_error_detectiontest IS
END final_packet_format_error_detectiontest;
ARCHITECTURE behavior OF final_packet_format_error_detectiontest IS
-- Component Declaration for...
:D.. I've oly been exposed to c++ and c.. i've just begun learning vhdl and verilog..
i'm aware that the state changes to the next state in this code everytime it comes across a rising edge.. i was asking if there was a technique to make it move across multiple states in one clock cycle...
@trickydicky:
Thanks a lot. I tried adding the reset, but realised i was adding another complication. i thought i could without adding it.
I'm posting the modified code, but i'm experiencing another challenge..
This is the modified code.
entity final_packet_format_error_detection...
@trickydicky: i need the byte_count to keep coming back to zero everytime a special byte is encountered. if i assign it to next_count in a synchronous process, will it do that?
when START_DETECTION => if( clock'event and clock = '1') then
next_state <= RECEIVE_DATA;
byte_count <= byte_count + 1;
else
next_state <= START_DETECTION;
byte_count <= byte_count + 1;
end if;
i removed the else condition. shouldn't that solve the problem? i also shifted the clock condition to...
entity final_packet_format_error_detection is
port (
data_receive: in STD_LOGIC_VECTOR(0 to 7);
clock : in STD_LOGIC;
special_byte : in STD_LOGIC_VECTOR(0 to 7) := "10000000";
no_of_bytes: in integer:= 3;
no_error_bytes : inout integer range 0 to 1024 ;
no_special_bytes ...
I have to write a vhdl code to accept inputs serially in the form of bytes(1 byte at a time). These bytes are in a particular order i.e they are received in packets where each packet is a frame with a specific number of bytes. This number of bytes in a frame can be defined by the user and is...
@sanju: thanks.. i'l try doin that..
@sanju and FvM:
okay.. i understood the reason for not being able to give two clocks in hdl.. but how do i go about programmin the code to do what i want it to do using state machines?..i don't quite get the logic framing..
Thanks for replyin promptly...
Oops. I corrected the entity error. But how do i go about with the structure of the program? i introduced the sub-clock to control the number of bytes allowed per frame. i am aware that verilog allows two clocks provided one clock is dependent on the other. the...
Sorry if the post is long, but i need urgent help in this regard. I have to write a vhdl code to accept inputs serially in the form of bytes(1 byte at a time). These bytes are in a particular order i.e they are received in packets where each packet is a frame with a specific number of bytes...
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