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Hi,
I need some ideas.
Attached is the result (a) of data sync circuit. In (a) clk2 is in-sync with data. I need to implement circuit (b) in order to create a pulse (c) when one of the clocks is in-sync with data. Any ideas how to do circuit (b)?
Thanks a lot for any help..
thanks all for the reply. what i exactly need is the one described by betwixt. Input A rising edge will make Y go high & input B rising edge will make Y go low.
chris.mourad:
i had the idea of clamping & have found similar design too..but i'll try your suggestion..
i had the hard time designing voltage reference that works in such a very wide range
supply voltage :( .. do you know any simple ckt structure how to regulate voltage?
mike.zhang: this is...
Hi chris.mourad
Breakdown voltage is 3.6V. I mean wide output swing opamp, perhaps still need to use this.
When ldo is in 6V supply, gate voltage of the power mosfet goes almost to VDD considering
no load condition. The output of the error amplifier will have breakdown issues since I can't...
Hi,
I'd like to know design considerations of ldo, this time operating in
wide range supply voltage (2~6V). Load current is just several
hundred uA. Do I still need wide swing opamp for this? How to
avoid breakdown?
Thank you very much for any ideas.
Ella
Circuit works perfectly fine without the iprobe having the same waveform in A.
And it makes more sense to me when checking the transient analysis. It is
easier to check stability when inserting iprobe while modifying or tuning results.
It began to bothers me when I tried to connect it in B. I...
iprobe is an analysis component in cadence when running stb analysis. compensation ckt
consists of RC network connecting error amplifier's output and Vout while another feedback
capacitors connecting Vout to the noninverting input of the error amplifer...
stability using B still shows...
Sorry. I haven't included the Cout in uF, Resr in mohm & load resistors in the
images. I'm actually using pmos as pass transistor. Currently, I am testing
closed loop stability using the instance iprobe in cadence. Initially, it is
connected like in A & stable. I am expecting the same...
which one is the correct way of measuring ldo stability
Hi All,
Why is that the ldo stability is different when measuring it in A & measuring it in B?
Which one is correct?
A.
B.
Thanks,
Ella
Right now,the one who requested the design has no specific application. Load current range(min.~max.) was specified but not with no load condition. That is why I wonder if it is always necessary to consider it. If we are given the required current range, say 100mA~200mA, do we automatically...
Hi All,
I would like to ask few questions to those who have already experienced LDO design. These are my questions:
1. Is it always necessary to consider the 'no load condition' of the LDO? Why?
2. If yes, what is a good circuit architecture of error amplifier needed when other devices (pmos...
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