Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
when i increase the dc voltage for the inverter , the amplitude of the spike goes up as well, is there a way i can eliminate common mode noise with any CM chokes or is board redesign required?
Observing this in both high and low side driver.
Im using normal oscilloscope probes (non isolated ) but im powering the oscilloscope from a battery powered UPS disconnected from the laboratory power liines
Attached the power supply and gate schematic.
Pos and neg rail meaning should i probe the power supply to the isolation transformer?
Thanks for the reply
The schematic is the gate drive . Im supplying the 15v through a pushpull configuration. when the inverter is not switching, there is no voltage spikes.when the inverter is switching , it induces a 40khz spike in the gate drive power supply which causes the gate voltage to the igbt to reach...
Hello,
I am building a high voltage inverter operating at 200v. i am using isolated gate drivers and the supply for the gate drivers (15V) is also isolated. But the inverter switching causes a voltage spike in the gate driver power supply . the spike is happening at 40khz which is twice the...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.