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Recent content by electronXwork

  1. E

    matching of current mirror

    I will only suggest a simple connection. If transistor A is the diode-connected transistor you can match them as Dummy,B(6), A(1), B(6), A(1), C(6), A(1), D(3), A(1), E(3), A(1), F(1),Dummy.
  2. E

    Help me with preparing a document with complete layout techniques

    Re: LAYOUT ASSIGNMENT I think it would be better if you use higher metals in routing signal lines than power lines. The noise injected by the digital blocks to the substrate might be coupled to the signal lines if routed by lower metals.
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    mixed signals circuit - layout advices needed

    mixed signals circuit Hi all, I am laying out a mixed signals circuit like audio codec so i am asking the circuit and layout experts to advice me what are the considerations i must take. thanks in advance....
  4. E

    Audio Codec layout considerations

    Re: Audio Codec layout How about for 4 channels?
  5. E

    Audio Codec layout considerations

    codec layout Hi guys, Can someone give me some layout considerations or techniques when designing Audio codec? tnx :D
  6. E

    Power line layout for AVDD line

    Re: Power line layout if for example in a ADC ckt I encountered AVDD3L, AVDD3R, AVSS3L, AVSS3R these lines are in the same ADC block. AVDD3L and AVDD3R are going to the same I/O pad same as for AVSS3L and AVSS3R. Do i still have to route them seperately going to the pad?
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    Power line layout for AVDD line

    Re: Power line layout Im sorry for the mistake on the drawing. the blocks are block1, block2, and block3 from top to bottom
  8. E

    Power line layout for AVDD line

    Re: Power line layout This layout is three metal process only...
  9. E

    Power line layout for AVDD line

    Power line layout Hi all, Please see the attached file for reference. Initially I layout A for AVDD line but I was requested to do layout B. In A, notice the vertical line, to save space I overlaped M1 and M2 w/ via12 on them. In B, I was instructed to have a dedicated AVDD line for each block...
  10. E

    What's the use of floating GP on PAD cell?

    Re: floating GP on PAD Yes, I also know that but I am wondering why do they need another signal to control the ESD Transistor of the pad. I have seen some circuits from the past having ESD transistors controlled by other circuits like the ESD connected to PDO of Charge pump in PLL but never...
  11. E

    What's the use of floating GP on PAD cell?

    Re: floating GP on PAD you are right the transistors are diode-connected because they are used as ESD for this PAD. But looking on the orientation of the floating gate I think it will not be possible for it to change the multiple of the transistor. if you have an idea i will really...
  12. E

    What's the use of floating GP on PAD cell?

    hi to all, While I am making a Chip layout I noticed the floating GP on the PAD standard cell. Can anyone tell me what are the use of these floating GP. Please see the picture. tnx
  13. E

    Where to start learning PIC on your own?

    Hi to all, I want to study PIC by my own. I just downloaded the simulator from mplab but havnt tried it yet. I have a background in electronics as well as in some programming languages. I also have a little bit idea on assembly language which I heard can be use in PIC. Please tell me where to...
  14. E

    Poly channel stop????

    Do you mean Channel stop implants?
  15. E

    Error when doing DRC/LVS: "nothing in layout"

    Re: Regarding DRC/LVS? For LVS- there might be missing instance or missing layout. Your netlist and layout are not match. There might be some elements that you forgot to put on your layout. For DRC- look on what device type it should have been and check the drawing rule if you have put all...

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