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Hi everyone,
I am very interested to know the Rds of the power transistor of a LDO.
But since the gate of the power transistor(PMOS) is generated by the error amplifier of the LDO, which is not always the lowest voltage, the Rds of the LDO doesn't depend on the power transistor size, but also...
Re: PSRR of LDO?
That exactly what I am confused about.
Let's say, if the error amp is shielded perfectly from the power supply ripple, than the error amp will have a stable output>> The gate of the power transistor is stable
But on the other hand, the source of the PMOS power transistor...
In general, to achieve good PSRR of a circuit, the circuit should be better shielded from the power supply, in other words, this circuit should better have a stable performance despite of the changing power supply voltages
But for a LDO, to get a good PSRR. I think this means that, when the...
Hello,
usually poly-to-Poly capacitors are used.
But sometimes, the capacitance between the gate the bulk of a transistor(bulk, source, gate are shorted) is also used a cap
I am thinking what are the differences between these two kinds of capacitors? Besides that the transistor needs less...
Hello everyone,
I am designing a LDO right now.
The cirucit works well in the AC simulation, there is sufficient phase margin.
But in the transient simulation, I set the load current as a variable which increases from 0 to 50mA as a pulse signal. When the load current pulse rises from 0 to...
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