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It was very easy to debug, after a day off. I grepped the LVS run directory for "sub!" and found the following two lines in the log file:
*WARNING* Programable terminal sub on I3 in cell cell schematic mySRAM, No property 'sub'.
*WARNING* Connection error: The instTerm. sub!, on instance I3 in...
Hi all,
I believe I am having a similiar issue. I'm trying to get a 6T SRAM cell layout Assura LVS clean using the cmrf7sf PDK. The schematic is a 6T cell with pin Vdd connecting to the pMOS sources and substrates, pin BL,~BL,WL connected as appropriate, and a pin for gnd connected to the...
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