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Recent content by Electric_Shock

  1. E

    PCB for testing a SAR ADC?

    Hi everyone. I would like to make a PCB for testing a differential SAR_ADC chip (designed in 180nm process). I wonder whether I need an input driver for my adc or just directly supply all the signal( Vin_p, Vin_n) from the function generator. About the reference voltage, I didn't design a...
  2. E

    Unable to plot the waveform while simulation in cadance specctre?

    I run a long simulation and want to plot the waveform while the sim is still running. But when I open Result browser and plot, there was nothing plotted. I have to wait until the simulation finish that I can plot the signal. How can I solve this problem?
  3. E

    Capacitive DAC layout in SAR ADC ?

    I have 2 options for choosing the MIM unit capacitor value in DAC. The option 1 is choosing the exact value Cu=24fF which has the size of 4 x 4.58 micrometer according to the calculation from Virtuoso. The other choice is a square capacitor of 4.5 x 4.5 micrometer whose value is 26.2405fF. Which...
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    Zero diagonal found in Jacobian error in simulation the DAC?

    I face with the problem Zero diagonal found in Jacobian when I run the simulation for DAC with bridge capacitor architechture. The error happens when I use MIM capacitor in the PDK. However, the simulation is run succesfully when I use ideal capacitor. How can I deal with this issue? I use IC...
  5. E

    Create a long delay with using inverter gate?

    Can you tell me some keywords related to this technique, The settling time of my DAC look very slow compared to other works although I tried to reduce the on resistance of the switch.
  6. E

    Create a long delay with using inverter gate?

    In my asynchronous SAR ADC, I need a delay of hundreds of nanoseconds for the capacitive DAC to settle. I realize that it is difficult to use the inverter chain to create such a big delay and it results in big power consumption and area. Is there any effective way to create such a long delay...
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    Voltage degradation in Hold mode of the bootstrap switch ?

    I have a problem with the bootstrap switch for ADC. In the sampling phase, output voltage can exactly track to the input voltage. However, when the CLK is low, the switch is off and the output voltage decreases by 3-4mV. The bigger the sampling MOS is, the higher the output voltage decreases by...
  8. E

    SAR logic design for 10-bit SAR ADC ?

    I have chosen a switching scheme for my 10-bit SAR ADC. But I am stuck at designing the sar logic control for DAC switch, comparator, S/H bootstrap switch. As shown in the picture is an example of 3-bit ADC. But my design is 10 bits and I need a synchronous SAR logic. I also review the knowledge...
  9. E

    Issue with bootstrap sampling switch ?

    **broken link removed** **broken link removed** I am designing a bootstrap sampling switch for ADC, but I have a problem that the voltage of Gate terminal of NMOS sampling switch is clipped when the vin is high. Vin is sine wave with amplitude of 1.8V, Vdd=1.8V, so the voltage Vg is idealy...
  10. E

    Problem with measuring dynamic figure of SAR ADC ?

    Ah. I see. I've just checked it. It actually 2.048Mhz when I set Y-axis to linear scale (in the picture is loga scale). Maybe I am confusing between the sampling rate of ADC(100 kHz or 100 kS/s) and the sampling rate of FFT(4096/1ms). Thank you very much.
  11. E

    Problem with measuring dynamic figure of SAR ADC ?

    Here is the my setting of fft calculator in virtuoso. The sampling rate 100kHz here is the sampling rate of my ADC, the testing input is 1kHz sine wave. I wonder whether I should copy the data and do FFT in matlab.
  12. E

    Problem with measuring dynamic figure of SAR ADC ?

    No, I used 1kHz sine wave input, sampling rate 100kHz. The FFT is 4096 point with rectangular windows
  13. E

    Problem with measuring dynamic figure of SAR ADC ?

    I design a SAR ADC and using ideal DAC (written in Verilog-A) to convert back to analog signal. I used 1kHz sine wave input, the sampling rate is 100kS/s. But the DFT of output looks so weird (in picture) which does not look like in some papers I read. Did I simulate in wrong way ? Please help me.
  14. E

    Pierce Oscillator simulation in Hspice ?

    I would like to simulate the Pierce oscillator in Hspice but I don't know how to generate a white noise in hspice environment. I also try .ic command to initialize for the circuit but it does not work. How I deal with this simulation ?
  15. E

    What do caliber PERC tools do?

    What do calibre PERC tools do ? Could anyone tell me what do PERC tools can do related to ESD perfomamce ? Can it plot a resistor map of all net in my circuit ?
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