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Recent content by elec_student

  1. E

    Samir Palnitkar verilog ebook

    verilog samir palnitkar I need samir palnitkar verilog ebook.
  2. E

    What is the clock jitter and how does it occur?

    What is clock jitter?? And what are the reasons for its occrrence?
  3. E

    What is clock uncertainity and why does it happen?

    how to decide the clock uncertainity Hi, Then what is the difference between clock skew & clock uncertainty??
  4. E

    What is clock uncertainity and why does it happen?

    Hi Guys, Can anybody explain me clock uncertainity and its reason?
  5. E

    Latch from a flip flop

    How to make a Dlatch from a D Flip flop??
  6. E

    Methods to recover setup and holdtime variations

    Hi, I have few questions : 1. What are the methods to overcome setup and holdtime violations? 2. What is clock uncertainity and the difference between clock skew and clock uncertainity? 3. What is "time borrowing" concept in latches? Please answer in detail if sumbody knows above questions...
  7. E

    Advantages of latch over flip flop

    Hi, Can anybody tell me some advantages of latch over flip flop except area advantage?? Also if sumbody can give some digital interview questions?? Thanks
  8. E

    RS Decoder Implementation

    rs decoder implementation I have to implement a RS Decoder, I would like to know how syndrome generation is performed in the RS Decoder and what will be the hardware implementation for the same. If anyone can provide any support document for the same it will be very beneficial. thanks
  9. E

    Accelerate design performance with HDL coding practices

    Hey I am facing negative slack in my design. I want some documents or tips which can help me in optimising code. This document was not helpful in this regard.
  10. E

    Accelerate design performance with HDL coding practices

    I am not able to open this pdf. Can u plese post it here?
  11. E

    Accelerate design performance with HDL coding practices

    Hi, Can anybody give me any support domuments or comments for the same. Thanks in advance
  12. E

    RTL optimization tips

    Hi, I am facing some slack problem while synthesis of my RTL. I tried optimizing but not to much effect. Can anyone tell from where I can get some insight of various optimization techniques for improving delay in combinational blocks. Thanks elec
  13. E

    Suggest me some references to learn synthesis concepts

    Re: Synthesis Kindly load any of the books u refer.
  14. E

    When masters initiate transactions, how do they go to each slave in AXI interconnect?

    difference between ahb and axi If more than one master is using same slave, then decoding is done based on priority. from Interconnect point of view, if more than one acces to a same location is done simutaneously then it needs to resolve conflict and pass only one request.
  15. E

    Suggest me some references to learn synthesis concepts

    abc for synthesis I am not able to access that website. Can anyone send me the material? Thanks
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