Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by ei99dami

  1. E

    Problem with synthesizing a divided clock

    I have a problem with the synthesize, when make a divided clock witch have both pos. and neg. detection on the clock. When a simulate it in questasim its ok, but not the synthesize. How do a do this work? -------------------------- -- Clock divider -- --------------------------...
  2. E

    Pulse width modulation

    To create a 4 bit pwm with a compartor to compare a counter with a ROM-table it will be 7 bits lower frequency (if detecting on both falling and rising edge on the clk else it will be 8 bits). Se attachment "pwm_scheme" on the scematic. I hope it can be done in another way. I´m going to...
  3. E

    Pulse width modulation

    I have problem to make a pwm with high frequency and high resolution. I´m using a internal clock of 160 MHz and I get a pwm of 1.25 MHz and a resolution of 4 bits. I have made my pwm by using a comparator a ROM-table and 2 counters. How do I do to make a pwm with higher resolution och higher...
  4. E

    Pseudo Random noise Generator in VHDL

    pseudo random noise generator Where can I find good information how to create a pseudo random noise generator in VHDL. /Robin
  5. E

    Pulse width modulation

    Can you please evolve what you mean with the PLL and how to implement the logic and set up your pulse pattern. /Robin
  6. E

    Pulse width modulation

    The FPGA is a Altera Stratix II or Virtex 4. The resolution for the 10 MHz signal is 2^8. (clk in to FPGA will be 2550 MHz) That will be a problem. /Robin
  7. E

    Pulse width modulation

    Hi, Is it possible to create a 10 MHz pulse width modulated signal from a FPGA? /Robin
See more

Part and Inventory Search

Back
Top