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what's mean of number of surface states under gate oxide?
for parasitic cap, I mean how did the metal over matched devices impact the Vth, the sigma Vth would be changed because of the para cap.
sometimes, for AMP layout, we must use power or ground metal cross all the matched mos, I know the best case is not cross any gate, for if metal cross gate, there would be para cap and will impact the Vth of mos.
so there comes a problem, if I have choice, which would be better if use...
Hi Thanks for your nice explanation.
there is one point that from current view, A is mostly better(2>1 situation as you descript, I am inclined to agree with you), another point that from lithography view, B is better, because A has 2 MT2 cross corner which B has only 1
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Could anybody help?
The best way is that once I have modified the layout, then I only need to run the script and it will auto export the gds/netlist and run lvs/drc, then I only need to check the result, anyone have any idea about this?
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