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Recent content by eejli

  1. E

    fundermental question about DFE?

    For DFE(decision feedback equalization),does it require that the input data of DFE being eye opened? I mean some small opening like Vpk2pk=100mV so that DFE can make decision. Or it does not require the eye opened but after the summing node the eye should be opened. Thanks!
  2. E

    a question about residual jitter after equalizor in serDes applicaions

    I recently know after RX equalizor, there is residual deterministic jitter of about 30 ps. Will this 30ps residual ISI be further rejected by CDR jitter transfer function? Since this 30ps is large, it will eat up a lot of jitter budget to pass the CDR jitter tolerance test. Many thank.
  3. E

    a question about CDR jitter transfer function

    Hi Folks, For clock and data recovery(CDR), Razavi's book says to design jitter transfer function to have low bandwidth to let the CDR loop to track the low frequency jitter from data input, and to reject high frequency input data jitter. My question is why not just design a high bandwidth...
  4. E

    clock and data recovery (CDR) loss of locking problem.

    Hi Guys, How are you doing? I am debugging my folk's CDR. The CDR can initially locked to the TX data in the right frequency, say 3 GHz. But after 20 seconds, the CDR lose of lock and lock to another frequency, say 2.97 GHz. After adjusting the CDR's VCO's tuning curve, the vco has multiple...
  5. E

    what is wrong with this matlab code?

    Hi Guys, I suppose to see more spectrum rather than 0 in the spectrum. Could you take a look on this code? I have a data file attached also. Thanks! ---------- close all clear all fs=5e6; npt=1024*4; double temp; double out; temp1=csvread('11cp001_ssc_PROFILE1_Math2.csv')...
  6. E

    If pll loop is open,why vco output eye diagram is closed?

    Hi guys, I have a on-chip PLL runing at open loop configuration,i.e., I broke the loop filter from the loop. And I just let the input of vco be connected to the board via a pin so that I can adjust the vco output frequency from the board. If I plug the vco output to a scope and see its eye...
  7. E

    how to decide vco gain (Kvco) in your PLL?

    kvco simulation frequency thank you guys. Yes I agree that Kvco should be small for spur performance. If Kvco is defined, then the charge pump current will be defined by the loop bandwidth assuming the divider ration is fixed and the loop cap is 100 pF for layout size reason. Am I right? Thanks.
  8. E

    how to decide vco gain (Kvco) in your PLL?

    vco gain I am wandering how to decide Kvco in the beginning of the design of your pll? It seems for me making Kvco from 1GHz/v to 100MHz/v does not make big difference since I always can find a loop filter to stabilize the loop. Is there other conditions that can bound the Kvco? Thanks.
  9. E

    what is wrong with this PLL loop filter?

    loop filter charge pump Thank you guys, The 72 uF is off chip on the board. This big cap value comes from the big vco gain Kvco_max=2.5GHz/V, charge pump current is 200 uA and divider ratio=200. I hope the loop bandwidth is about 500khz. I plug in this numbers in a ADS program, and it comes...
  10. E

    what is wrong with this PLL loop filter?

    pll loop filter Dear Folks, I am testing my PFD, charge pump and loop filter. They are connected in series. As shown in the attached figure, the loop filter voltage drop down after the increasing ramp when "UP" signal =1. Where does this voltage drop come from. I am using ideal resistor and...
  11. E

    how to define vco gain,Kvco in the PLL loop analysis?

    pll loop analysis I am wondering how much Kvco is adequate in my vco design. How is it related to other important specifications of the vco such as phase noise, loop stability? My second questions is for the traditional cross coupled LC vco, what is the vco gain formula in terms of tank L and...
  12. E

    mixer LO to IF port leakage problem.

    yes, the chip has a low pass filter after the mixer. My concern is what kind of issue the big LO leakage could have though it can be filtered out after the mixer.
  13. E

    mixer LO to IF port leakage problem.

    My chip has a measured LO leakage at the mixer IF output. It is in worst case only 25dB lower than the desireable IF signal. what could be the reasons and what is the bad side of this leakage? Thanks.
  14. E

    Is there any good EDA tool for simulating RFID system?

    ADS. You can use WLAN examples to construct your own RFID test bench.
  15. E

    how to know whether the ASITIC inductor modeling is right?

    asitic inductor For the PLL, I use ASITIC to model the onchip inductor in vco. How to know whether the modeled inductor Q is right by measurement? I think the VCO Q is different from the inductor Q. Thanks.
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