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hi,
How to balance the PLL bandwidth with free-running frequency?
I saw people said that usually PLL bandwidth is much less than free-running frequency, WHy?
Thanks
Hi,
Thank you for watching this post.
For a simple feedback, like R1=R2=R, OPAMP's gain is A.
Non-inverting feedback amplifier, the input impedance is (1+AB)*Ri, B is feedback factor.
Inverting feed amplifier , the input impedance is R+R/(1+A)
I can do some math to get the...
Re: Help to analyze the Gain-by-2 switched cap based Amplifi
thanks,
That is what i am thinking, why it's not symmetrical. It's obvious caused by OTA.
Is it because OTA has different discharge and charge cap?
Best
hi,
I am designing a 1.5 bit Sub-ADC. The Gain-by-2 Amp is shown in the graph below.
The sampling speed is 200MHz, Supply is 1.2. The waveform is only Gain-by-2 Amp result. the input is 300mvP-P. And the ideal output waveform should be 300mv--900mV and DAC output is fixed at 600mV.
Gain of...
hi,
I design a bootstrapped switch used in a simple sample/hold circuit( a bootstrapped switch with a cap load).
The bootstrapped circuit and simulation result is in the following graph.
In the simulation, the blue line is a ideal switch result. the red line is using a bootstrapped switch...
thanks.
But should be V1P and V1n equal to Vcm ?
best
gang
Added after 5 minutes:
thanks. I still have a little confusion.
If thing comes to
V1p -V1n = (Vin+ - Vin-) + (Vc+ - Vc-) - Voffset
Whey there are still the same?
if we assume reference direction is fixed
Best
yeah, just as a normal switch used in switch cap circuit like Sample/Hold.
Added after 5 seconds:
yeah, just as a normal switch used in switch cap circuit like Sample/Hold.
Added after 2 minutes:
Thanks.
How can i know the requirements to define allowable leakage to not-fail the...
hi ,
I am designing a MOS switch.
There are three types of threshold Voltage MOS, Low Vth, Normal Vth,and High Vth.
As i know, low vth can run high speed but large leakage. High is low speed, small leakage.
In the mos switch design, do you care about leakage ?
Best
Gang
hi backerShu,
Thanks for your reply.
What i don't understand is why Vin+ - Vc+ not Vin+ + Vc+?
when i design charge pump, if you give a Vdd to Cap, it will boost the output.
best
Gang
hi,
I read the auto-zero comparator, the first stage is to stage the offset error(top graph)
And the second stage is to compare Vin and Vref, which will eliminate the error( low graph)
I have question on the equation on second stage. Why (Vin+ - Vin-)- (Vc+ - Vc-)?
Could you anyone help to...
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