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Recent content by eebug

  1. E

    A website for ee related question discussion

    www.eequestion.com Welcome to post your questions there. It is currently in Chinese. I am considering whether it would be good to make it in Englisth.
  2. E

    slew for clock nets and signal nets

    I guess it depends on the requency. More important it should be compliant to the design rule required by technology. for setup check you normally apply slow slew rate, for hold check fast slow rate. Also some pads need slow slew rate in order not to introduce too much noise.
  3. E

    Why the code coverage of modelsim6.5 and IUS82 are different

    ius code coverage I run the same case using IUS82 and modelsim6.5, but got different code coverage. IUS82 for block and expression; modelsim for branch and expression. The expression coverage of IUS is a little bit higher than modelsim. What's the reason? Thanks,
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    about sigma delta filter bit-wdith

    sigma delta filtering I am working on a Sigma Delta ADC project, and need to decide the bit-width of the digital filter. My filter has 4 stages, the first is CIC and the bit width is 29 bits according to the OSR. My final filter output is only 24 bits. So this means the other 3 FIR filters need...

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