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Recent content by ee_wmxaa

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    Verification using Design Analyzer (Verilog)

    Hi, I have a problem using Design Analyzer. When I using DESIGN OPTIMIZATION, I set MAP DESIGN to high, VERIFY DESIGN to high, ALLOW BOUNDARY OPTIMIZATION. The program will run in a very very long time, (~10 hours), then fatal error. If I set VERIFY DESIGN to low, then after around 10mins, the...
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    DC offset cancellation in VGA (Variable gain amplifer)

    dc cancellation Hi,vfone Can you tell me more detail about why the bandwidth will look like a bandpass filter. Thank you:)
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    DC offset cancellation in VGA (Variable gain amplifer)

    dc offset cancellation Hi,all I am doing a project on designing a variable gain amplifier (VGA)under UWB specification. I have conducted several literature research. I found that they included a dc offset cancellation circuit in most of the previous work. And after adding this circuit, the...
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    DC offset cancellation in VGA (Variable gain amplifer)

    dc offset cancellation Hi,all I am doing a project on designing a variable gain amplifier (VGA)under UWB specification. I have conducted several literature research. I found that they included a dc offset cancellation circuit in most of the previous work. And after adding this circuit, the...
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    Extract Problem in LVS - 1 cells has 1 label short problems

    Extract Problem in LVS There is no such NMOSCAP_PC1
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    Extract Problem in LVS - 1 cells has 1 label short problems

    Extract Problem in LVS In the tsmc18rf lib, there are no such nmoscap_PC
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    Extract Problem in LVS - 1 cells has 1 label short problems

    Extract Problem in LVS The above diagram shows a nmoscap. The upper node is the G, the middle one is called B, the lower one is S. As you can see there is no D, and B and S are already connected to Vss.
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    Extract Problem in LVS - 1 cells has 1 label short problems

    Extract Problem in LVS I have the following error message. But I do not have a cell called nmoscap_PC1. Also, how to locate net "C1"
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    Extract Problem in LVS - 1 cells has 1 label short problems

    Extract Problem in LVS Hi,erikl I am sorry for the typo in the previous message, it should be "There are 'no' two pin label with the same name " The problem wasn't solved yet!! Actually, I am using tsmc 0.18um process. The cap I used is NMOSCAP. I also run a LVS simply check the capacitor. No...
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    Extract Problem in LVS - 1 cells has 1 label short problems

    Extract Problem in LVS Hi,erikl This label short problem is found on the capacitors layout of the circuit. If I removed all the capacitors, this label short problem will also gone. There are no pins connected to the capacitors. And I have checked there are two pin labels with the same name.
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    Extract Problem in LVS - 1 cells has 1 label short problems

    assura label short problem Hi, everyone. I was doing LVS check recently, I found my schematic and layout matched in the "compare" window, but in the "extract" window (also in the LVS result window), I found a short problem. In the summary file, it said "1 cells has 1 label short problems". I do...
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