Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Dear Sem (or maybe not Sem),
Thank you very much for your reply. Your statement seems to be in accordance with what the spectre HDL compile complains about. However I have no clue how to pass the VCDC-module to the VCDL-module without using the "`include"-statements. Could you provide in a...
Dear edaboard members,
I am new to VerilogA and I have a question related to the Spectre VACOMP-1047 warning. I am trying to fabricate a Voltage Controlled Delay Line (VCDL) in VerilogA which is build up out of Voltage Controlled Delay Cells (VCDC). I include the VCDC into the VCDL to make...
Hi
I'm making some code and trying to use genvar but Cadence gives some error back. I suspect what the problem is but I'm not sure. Furthermore I hope someone of you encountered this problem before and has knows a workaround
The code is a little complicated and a there is a lot of stuff in it...
Hi all,
I'm implementing a SPAD model(base on: SPICE modeling of single photon avalanche diodes. by F. Zappa∗, A. Tosi, A. Dalla Mora, S. Tisa and published in Sensors and Actuators A 153 (2009) on pages 197–204) and the problem is in a swith out of the analogLib of Cadence (in combination with...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
