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Recent content by edinburghtech

  1. E

    Line driver for PDM digital signal

    Hello I am trying to wire up a PDM microphone (SPH1668LM4H-1) to an MCU board. The cable length is 40 inches twisted pair. Please suggest a suitable method for buffering the PDM clock and data to/from the mic to mcu. I am unable to find an IC designed for this purpose. Thanks Edintech
  2. E

    Loading of bias node by transmission gate

    Hi Erikl Thanks for the reply This solution might work, however i am not sure if using minimum size TGs will have any other issues. Any ideas here? Thanks Edintech
  3. E

    Loading of bias node by transmission gate

    Thanks erikl. I agree to your solution. However this involves including an opamp stage in between. Any tips on FET sizing in transmission gates to avoid loading?
  4. E

    Loading of bias node by transmission gate

    Hi I have 2 bias voltages generated by a current source. These bias voltages are used to selectively bias many transistor gates. Selection is done using transmission gates. When number of transmission gates connected to this node increases, the bias node gets loaded and bias voltages falls. Any...
  5. E

    Cascode transistors in CMOS design

    Re: Explanation of DC operating point parameters Hi Erikl Thank you for the help. I have one more question. Is there any way I can reduce the drop across the cascode transistor (Vds without changing its W/L or not touching the Vdd? Please let me know. Thanks Tech
  6. E

    Cascode transistors in CMOS design

    Re: Explanation of DC operating point parameters Hi Erikl Thank you for replying Please correct me if I am wrong If M1 is current source and M4 is Cascode (My circuit https://obrazki.elektroda.pl/1809141300_1375520932.png) To increase Vds of M1, increase L1, which means I should increase...
  7. E

    Cascode transistors in CMOS design

    Re: Explanation of DC operating point parameters Hi Continuing with the discussion In a cascode current mirror I designed, the power supply is fixed ie total voltage across drain- source of both cascode and current source transistors are fixed. At the moment, I have 300mV across cascode and...
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    Cascode transistors in CMOS design

    Hello Everyone Thanks for your reply. I understood it now. I have adjusted sizes so that for my cascodes, Vgs > Vt and Vds> Vgs - Vt now to be in saturation On a different note, is there any way i can find details about the dc op points that cadence prints out. For example terms like vgt...
  9. E

    Cascode transistors in CMOS design

    Hi I am having a cascode current mirror. I have ensured that current source transistor is in saturation. I was wondering, what will happen if one of the cascode transistor move to linear region? Please let me know Thanks Tech
  10. E

    Current mirror matching for DAC

    Hi Erikl Thanks for the reply. Since my required resolution is 10bits, as you mentioned the matching should be atleast 1/2^10 = 1/1024 = 0.1 % right? I am unable to find corresponding literature in this area. I will try to check each and every output point as you mentioned. Also could you...
  11. E

    Current mirror matching for DAC

    Hi Can some one please help me understand the current matching requirement related to the resolution of a DAC. For example, if I am designing a 10 bit current mode DAC, how well the currents should match (Current through bias network is 100uA) . Also please suggest me some books/papers from...
  12. E

    Differential pair input

    Hi I am designing a current steering DAC in which a current cell constitutes of a current source, cascode and differential pair. Digital input comes to the differential pair which causes the current to be channeled through either of the branches. At the moment the input of the differential...
  13. E

    Maximum current in CMOS

    Hi I have a fundamental question (might be dumb). I know square law relates current to W/L and overdrive. But is there any thing that limits the maximum current that can pass through a transistor. For example I can pass 10uA through the transistor with say a W/L = 5u/1u , can I pass 100mA...
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    Verilog A -- Differential Equation

    Hello I am electronics person with very little knowledge of verilog A. I am trying to model a diode in verily-A at device physics level. This includes dealing with various differential equations (handling recombination of carriers). Can any one please guide me to an appropriate location or tell...
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    Verilog-A Modelling of Diode

    Hello I am trying to use Verilog-A to model a diode. This model will be attached to a spice netlist and simulated in spectre. I want to know if its possible to code the model in such a way that it behaves different to different simulations. (DC, AC, TRAN etc ). Please advise Thanks EdinTech
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