Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
I have mentioned two statements here. Somebody please explain the 2nd statement. Also what are the consequences if we connect a gate supplied by a higher voltage to a gate supplied by a lower voltage?
1. Level shifters are required when a lower voltage signal drives a gate supplied by a...
Hi morris_mano,
Thanks for your answer. For more clarity, I would like to elaborate the question 4.
4. In a design, a single scan chain (running with same test clock) can be used to stitch FFs running with different (functional) frequencies?
From your reply I assume the answer is yes. That is...
Hi,
With scan_mode sdc, how the clock balancing is done in Physical Design?
Because, there might be different functional blocks running with different frequencies in a chip and the at-speed clock will be the highest frequency clock.
My discussion points are,
1. During capture mode, low...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
