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Recent content by eda_heat

  1. E

    import EDIF file into Cadence

    importing and exporting a design cadence Do you make sure the Cohesion can export the design by EDIF? It seems it only can export the symbol by EDIF format.
  2. E

    [Help] ADC or DAC measure for HSPICE

    You can use the sandwork to read the HSPICE simulation result and use the ADC analyzer in sandwork to do those measurement.
  3. E

    Circuit simulator for linux

    You can use the mixed-signal simulation flow by modeling the verilog in digital simulator and modeling the verilogA simulator. For example, ncsim+hsim or VCS+nanosim/hSPICE
  4. E

    How to run simulation with mixed-signal design?

    You also can use hsim + ncsim
  5. E

    analog circuit - what is phasemargin and gainmargin?

    analog circuit You also can get the "MOS_op-amp_design.pdf" at hxxp://engr.smu.edu/ee/7321/MOS_op-amp_design.pdf
  6. E

    how can I get the document in verilog-a

    hxxp://analog.ee.washington.edu/pdf/veriaref.pdf hxxp://ece-www.colorado.edu/~ecen5007/cadence/files/veriaref.pdf
  7. E

    Anyone familiar with Mentor's Eldo?

    Humungus, Thanks for your explanation. HSPICE doesn't have this feature. It seems your examples also can use the calculator to get the answer. What are the advantages for this Eldo's special feature?
  8. E

    Anyone familiar with Mentor's Eldo?

    eldo forum mentor Does any one know how to use "Set Safe Operating Area"(.SETSOA) Eldo simulation control deck? Is it useful? What situation will use it? Thanks,
  9. E

    How to make sure the op-amp is correct??

    Where can find some test circuit examples to demo how to measure these amplifier specifications? Thanks,
  10. E

    Looking for tutorials or references about VHDL AMS

    VHDL AMS You also can read the IEEE Std 1076.1-1999 (VHDL-AMS LRM)
  11. E

    Looking for tutorials or references about VHDL AMS

    Re: VHDL AMS The attached file is a tutorial for "Analog and Mixed-Signal Modeling Using the VHDL-AMS Language"
  12. E

    tools and languages for AMS design

    From tool supporting view, it seems more tool supported the verilog-AMS than VHDL-AMS. Another view, right now the spice +verilog-A + HDL simulation environment is more popular. Maybe it is also a good solution to do the Analog Mixed-Signal simulation.
  13. E

    Full custom IC design Concepts

    Is this document same as one in Taiwan's CIC?
  14. E

    Generate Hspice Netlist from Cadence

    generate hspice netlist in cadence 1. For "modeln" model name, you can edit the mos device's object property. Put the "modeln" to the "Model name" field. 2. For generated a hspice netlist, you can invoke the "Analog Environment" by "Tool->Analog Environment". . Set the simulator to...
  15. E

    Where should I start with?

    You can search an ASIC tutorial material and study it first. There are many IC related lectures in university class. You can use the goolge to find them.
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