Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by Eceraj10

  1. E

    Matching techniques in diff pair and current mirror??

    any body help me in that matching techniques of how to match diff pair and current mirror in Analog layouts???
  2. E

    what is meant by parasitics in analog layouts?

    i am new to analog layouts? can anyybody help what is the parasitics &how to reduce parasitics in analog layouts??
  3. E

    how to prevent the ESD in cmos layouts?

    yes absolutly correct, timof:) ya that is my correct intention of "how to protect ICs against ESD events"can anyone explain pls..
  4. E

    how to prevent the ESD in cmos layouts?

    what is the methods using toavoid ESD in CMOS layouts? anybody explain clearly?
  5. E

    matching the transistor

    can you give some examples method for matching the transistor?
  6. E

    current density in analog layout

    thanks for your kind replies...it is very very useful for me.. can anybody reply more technical to avoid current density problems in cmos layouts?
  7. E

    matching the transistor

    can u tell ..technical reasons pls..why we need matching in transistors?
  8. E

    matching the transistor

    ya sure transistors only..matching of transistors in IC layouts...
  9. E

    matching the transistor

    can anybody help me?why matching requied in ic layouts?explain clearly
  10. E

    current density in analog layout

    what is the current density in the analog layouts? can anyone helpme pls
See more

Part and Inventory Search

Back
Top