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Recent content by ebrahimi.khoy

  1. E

    Static Timing Analysis in the presence of Process Variation

    I need to have the distribution of critical path delay. With this technique, I can get delay for three corner cases (min, typical, and max).
  2. E

    Static Timing Analysis in the presence of Process Variation

    Is there any method to compute the critical path delay in the presence of process variation? Which tool uses this method and what are the inputs? Thanks in advance for your answers.
  3. E

    Bound a register to specific type of flip-flop in Design Compiler

    Hi, I have two types of DFF in my library. How could I force design compiler to use a specific type of flip-flops for some registers? For example for program counter, I intend to you type 1. Thanks in advance for your help.
  4. E

    How to specify space between cells in SoC Encounter

    Thanks for your replies. Let me clarify the question with an example. Let assume that there are 10K gates in my design. I analyzed them and I find those that if placed close to each other, they increase circuit failure probability (due to soft errors). Now, I want to have at least 10um distance...
  5. E

    How to specify space between cells in SoC Encounter

    Hi, I have specific pair of cell instances in my design that should not be placed very close to each other? Is there any way to specify the spacing between specific cells?
  6. E

    Deterministic Results with Design Compiler

    Do you remember the paper title for that presentation?
  7. E

    Deterministic Results with Design Compiler

    Is there any way to adjust this seed?
  8. E

    Deterministic Results with Design Compiler

    This is not true for Design compiler. I guess they implemented an stopping condition based on the time. Since the timing is dependent on the other running tasks, it become non-deterministic.
  9. E

    Deterministic Results with Design Compiler

    I run synopsys design compiler for a relatively large processor core and every time I get a different netlist. Is there any why to get deterministic results from this tool?
  10. E

    How to create a long delay with small power

    Hi, I need to create a long (500 ps) delay between 2 flip-flops while the delay of inverter is about 10 ps. My current implementation is an inverter chain with 50 cells. Is there any other solution with less area/power overhead? Regards, Mojtaba Ebrahimi
  11. E

    How to extract ICECAPS technology file?

    Hi, I need to compute the post-layout power consumption in SoC Encounter, however, for creating power grid libraries it requires an ICECAPs technology file. I am using TSMC 65 nm general purpose standard cell library. Does any one have some experience in dynamic power analysis with SoC...
  12. E

    How to estimate the temperature of a design after place & route?

    Hi, I want to estimate the temperature of a circuit after place and route by cadence SOC encounter. I am able to run some workloads on this tool and extract switching activity and then extract power from synopsis power compiler. Considering these, does anyone know a solution to estimate the...
  13. E

    Zero width glitch in VCD file

    You should register at here **broken link removed** After registration, you can download it for free.
  14. E

    Zero width glitch in VCD file

    I was using Nangate standard cell library and there was a problem in this library. In fact there was some sort of feedback in some cells and modelsim does lots of iterations on these loops. I removed them and problem solved. Are u using Nangate for synthesis?
  15. E

    oa2cdb and Nangate Library for clock tree synthesis

    Hi, I am doing clock tree synthesis using Nangate Library. Every thing is OK until the step that I want to extract spice netlist of clock tree. In this step, it asks for cdb file and I found that I should create this using cadence oa2cdb tool. I was not able to create the cdb format using this...
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