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Thank you.
So, as I understand, if our customized adder results in better synthesis DC automatically choose our adder.
Just one more question: How can we change the objective function to only include area?
I want to generate a netlist for a non-hardware application. I am actually interested...
Hi,
I am using Synopsys DC for synthesizing Verilog code to gate level netlist . I have designed a customized adder and I want it to be used where there is addition in my functional Verilog code, e.g.,
wire [N-1:0] a,b,c;
assign a = b + c;
Right now, it seems DC uses DW library by default. How...
Hi,
I got the Loop exceeded maximum iteration limit. (ELAB-900) error in synopsys design vision. I am aware that it is not a proper usage of for in verilog. I am trying to generate a large combinational logic, that's way I need to use for loop in always@(*) statement.
I was wondering if...
Hi,
I write a custom library for synopsys design vision which only consists of XOR, NOR, and IV (inverter or NOT). My plan is to synthesize a combinational logic such that the resulting netlist has minimum number of NOR gates. I write the library as flows:
library(and_or_xor) {
cell(NOR)...
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