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async double sync flop
Can someone suggest a book that covers this subject and other similar dubjects? I don't think I'll find it in my digital logic design book.
Thanks vomit, there was no `define statement in that file, I guess it can be in another file.
I still don't know the answer to the other question, what's does this (1 << `set_size) do?
Hi,
I'm learning Verilog and I have questions, I'll put them in this thread and your help is appreciated, questions in red are still not aswered, questions in blue are answered. I'll add the answers in this post so others can easily find them.
1- What does it mean when a variable is preceded...
I know for amps, you have to look for Miller capacitance (C) accross which there is the largest gain, then very often the dominant pole is 1/(A*C*R), A and R are the gain and resistance accross C, assuming A is large. For a common source, C is Cgd, for a two-stage op-amp, C is between the...
Hi,
Can someone please suggest a practical book (or anything) on synthesis, that explains timing constraints and optimization? Is this a good book for this purpose:
https://www.amazon.com/exec/obidos/ASIN/0137943482/qid%3D1124319545/sr%3D11-1/ref%3Dsr_11_1/102-9701514-5995354
The...
Re: Fastest Inverter
-One way is to use cascaded inverters as in the book: Digital Integrated Circuits: A Design Perspective, page 206-210 (2nd Edn), if the output capacitance is large, this should speed up your clock_bar.
-Make the clock rise and fall time 10ps.
-Another way is to use a...
Hi,
I'm learning Verilog on my own right now and I'm stuck, please help. I'm confused how arrays are referenced. Here's the code that confuses me:
//first, the declarations, I have no problem with them:
input [width-1:0] data_in;
input clk, reset;
output [width-1:0] data_out;
reg...
Hi Robert,
Your PLL is locked as long as d(ΔΦ)/dt=0, and Δω=0, so congrats. Regarding the difference in Vcontrol, this is most likely because your standalone VCO sees a different capacitance than when it is in the loop, so just follow it with the next stage to get an accurate Vcontrol.
Hi Robertt,
The corner frequency has to do with the noise in the transistor. Noise is modeled by referring it to the input, then assuming that the transistors themselves are noiseless, then fc it is simply the frequency at which this "input referred" voltage noise source is no longer dominated...
This was one of my projects last quarter, we used an Alexander phase detector (full rate), V/I converter (can be found in one of Razavi's papers), LC VCO. I don't think this is good enough for a company though, as there is not much frequency detection. We used CML based circuits driven with...
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