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Update: I used a different FPGA output pin - different bank - and got a slightly better clock.
Without a capacitor
with a cap
But I still understand why the cap changes the clock in this way and if whether this is a valid solution.
As promised... These were captured at 1GHz using the TPP1000 (1 GHz , 3.9pF / 10 MOhm) probes
System startup - only clock output (no instruction to generate samples). Yellow trace = clk FPGA side, Cyan = clk DAC side. Big difference.
While also sending samples (purple line= DAC out)...
@Klaus I would avoid using the caps if I could find a better solution. I am sorry but I don't understand what you mean clock_return. Do you mean the negative edge? The clock that goes to the DAC is 180 to the one that drives the logic (and samples). I've also tried 90 and 270 degrees offset with...
Dear Klaus,
Thank you for your reply. I am aware that 275MHz is borderline fast for single ended signals. But the boards are rated (I am using an evaluation board for a 275MSPS DAC) for these speeds so they should in theory work. I have links to both boards in the original post.
There are more...
Dear all,
This is probably not the right forum to post my issue, but it is seemed to be the most relevant.
I am interfacing a Xilinx ML506 board with a texas instrument parallel TI DAC evaluation board using a breakout board I designed. Both boards have header rows which I match on my pcb...
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