Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Re: OFDM synchronization
Hi!
You can start from the book: "OFDM Wireless LANs: A Theoretical and Practical Guide" by Juha Heiskala and John Terry.
The Book's chapter 2 is about sinchronization. The synchronization problem was not reviewed so widely, some important details was omitted. But for...
addition in vhdl
Hi!
Just add:
1. Use Ieee.std_logic_unsigned.all;
2. en: in std_logic;
3. you have to extend a(0), a(1) etc to 4bit by "000"&
Have a nice day!
Library IEEE;
Use Ieee.std_logic_1164.all;
Use Ieee.std_logic_unsigned.all;
entity add is
Port(
a: in std_logic_vector(3...
Hello!
I'm interesting in algorithms and structures of interference cancellation system for wireless repeaters. Who can recomend me some sources (book, papers, links) about it.
Thanks
Re: State machines
Hello!
My last project required FSM (Mealy) with about 100 states. Implement it as one large FSM – it’s not good idea. So, i have splitted it on 4 small FSMs – main FSM and small subFSMs. I agree with lucbra, what more than 16 states is large FSM.
Using this approach you...
xl_state function
Hello!
More detailed information about xl_state you can find in Matlab help about Xilinx SG component MCode:
1. find component Simulink/Xilinx Blockset/Control Logic/MCode
2. open help about MCode
3. In that help you can find information about xl_state
P.S. As for me, MCode...
Re: VHDL Code problem
ModelSim simulates and compiles the next code correctly, it works:
library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity UART_CLK is
port (
clk : in std_ulogic;
rst : in std_ulogic;
CLK384 : out...
Hi!
If r3 is register, you have to put it on process! In other case it will be latch.
process(clk,reset)
begin
if reset = '1' then
--reset r3
elsif (clk 'event and clk '1' ) then
if flag='0' then -- if flag asserted
-- shift r3 instance
end if;
end if;
end process
Have a nice day!
Hello!
CSwitch Corp. has announced new FPGA design methodology and new FPGAs. Proposed approach sounds promising: “Narrowing the performance and density gap between FPGAs and structured or platform ASICs, a novel configurable array architecture un- veiled by startup CSwitch Corp. promises to...
Hi!
Tools and language usage depends of design's starting point. For most designs the VHDL or Verilog is enough. But, if design starts from high-level, then HDL only language usage is not convenient. We have to use also different tools (and languages):
* If starting point is Matlab, you can try...
8 point fft vhdl
Hello!
Radix-4 is a good choice for FFT implementation. At first, you have to decide, which architecture is more suitable for you: pipelined or literal. In computer books exists many FFT processor architectures – you have to select best one for your application. Using the...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
