Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Re: DC synthesis of sync D-flip-flop maps to unnexpected flo
Sorry, my mistake while copying and pasting the code. Not sure if it had to do w/ the emoticons or something...
Anyway, the definition of 'd' and 'e' should be read as in :
input [1 : 0] d, e;
reg [1 : 0] e;
It turns out DC...
Re: DC synthesis of sync D-flip-flop maps to unnexpected flo
The problem I'm having is reproducible w/ the class.db technology library distributed along w/ synopsys design compiler.
I have a very simple synchronous, active-high reset D-flipflop, which I expect to have it mapped
to the...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
