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That's what I did in VHDL.
Was just thinking whether by specifying range 0 to 9 will cause it to cycle within this range.
Found that it doesn't work this way so will have to check in the code using IF statements as above.
Thanks nonetheless.
Hi,
I wish to implement a counter with a range say from 0 to 9. Is there a way to specify the range such that it will be only within the range 0 to 9? For example, if I use counter<=counter-1
The current counter value is 0 and I wish the subtraction to yield 9 instead of -1 automatically...
what is the implication of using the following package?
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
thanks.
Hi
I'm new to VHDL so please pardon my "silliness".
when I declare a signal (signal_a) as std_logic_vector and I wish to check for sign, is the statement below valid?
if (signal_a>=0) then
or should I specific the MSB explicitly:
if(MSB of signal_a ='0' )then
Thanks in advance.
ps2 keyboard vhdl
Hi,
I'm a newbie to FPGA and VHDL. As part of my project, I'm thinking of capturing the input from the keyboard through the PS2 port of Spartan3E. I've tried searching through the reference design but to no avail. The idea seems to be to capture the 11 bit bus together with...
xilinx ise tutorial
Hi
I'm trying to use VHDL to display on the LCD of Spartan 3E. Appreciate if Peter or anyone can provide me some resources too. Thanks.
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