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Hi
Can anyone tell me in detail what are the advantages ofa charged pump type PFD as compared to a Phase detector?
Thanks
PS: got exams on sat..plz help
HI
I am looking for a way to implement a simple BPSK modulator and demodulator in VHDL, but could not find any prewritten code to learn from on this topic.
Can someone help me in regarding to this.
This is for my Project.
Thanks
Thanks xxargs,
but somehow i couldnt grasp what you were saying...probably our english dont match.
secondly i am not working on pll design or rf
just that in the top level chip floorplaning i have some pll blocks which need to be connected with power pads
only guideline for me is that this...
DSP HELPPP!!! Plz
Hi guys,
I am a comp science grad and have taken DSP as a course in my MS program. With 10 days left for my exams my prof asks me to wrap up on control engineering basics from some good book.
Can you please tell me which topics in control engg will help me in DSP and which...
Thanks a lot mate.
Actually i am using cadence First encounter for routing. Now for doing manual routes for PLL's i was told to do routing in star formation.
So thats why i was totally confused as to why this requirement was there.
If any one else can comment it would be very much appreciated
Re: Nanoroute Problem
hey
correct me if i am wrong but you can do CTS only in Astro...so you must have taken post CTS Def from astro...PC is just a placement tool...right
also is FE showing this error only for this one instance or any other instances?
Hi,
I have a doubt regarding Star formation and Delta formation of resistances.
Can anyone explain whether the resistance is more in star formation or delta formation of res? also is there any good doc on this.
I heard star formation has res = r +r +r
and delta has it res = 1/r +1/r +1/r...
Re: required design flow?
i doubt if you can take Def into icfb
take the vhdl/verilog to phisical deisgn and dump a gdsii .
you can use icfb or calibre drv to view the gds
Can you elaborate on what exactly you want to know about cadence tool.
I work on cadence First encounter at my workplace.
You first start with floorplanning of you top level Chip or block level Module.
Floorplanning is creating the physical dimensions for the chip/block, Placing custom macros...
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