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dpaul81

Recent content by dpaul81

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Look up table for sine wave generation

I agree with you! I had used it as a simulation model only. Something like a soft fn. gen for my other modules.
- dpaul81
- Post #8
- Mar 25, 2014
- Forum: ASIC Design Methodologies and Tools (Digital)
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Look up table for sine wave generation

Hi, I had used this in an internship project for sine wave generation and was very successful. No need of implementing look-up table and stuff! You can generate a sine wave using Maclaurin series equation and using up to only 3 terms in the equation. The maximum error percentage between an...
- dpaul81
- Post #4
- Mar 24, 2014
- Forum: ASIC Design Methodologies and Tools (Digital)
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[SOLVED] OpenSource Tool for creating Timing Diagrams

After searching for hrs & a comparative study, finally got a one which is free! Also u don't have to write scripts to genetrate waveforms.....just fill out a few blank spaces & lo.....ur waveform is generated! I would recommend it to all who r looking for a free version! introduction...
- dpaul81
- Post #4
- Apr 8, 2011
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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[SOLVED] OpenSource Tool for creating Timing Diagrams

Hello all, Can anyone suggest me a good OpenSource Tool/Package/Editor for creating timing diagrams? It can also be in a format where one can write a script and then the waveforms are generated on compilation! The most important thing for me is to save my current work in a format which can be...
- dpaul81
- Thread
- Apr 8, 2011
- Replies: 3
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Use of 'inout' ports in Verilog

Hi....thanks for the reply! I got my code working! But now I am facing a problem in the testbench! Since I am having inout ports, so what corresponding mapping must I have in a testbench? (For normal in or out port, Verilog says that in a testbench, these ports must be driven from a register...
- dpaul81
- Post #3
- Mar 31, 2011
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Use of 'inout' ports in Verilog

Hi all, A digital unit has two buses both of them are 32bits wide (say bus1 & bus2) and can either Rx or Tx data, so I am declaring them as INOUT ports in Verilog. There are also some signals, and according to their conditions data has to be moved from bus1 to bus2 or bus2 to bus bus1. Can...
- dpaul81
- Thread
- Mar 30, 2011
- Replies: 3
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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blocking and non-blocking statements in verilog?

A quick explanation from the useage point of view...guess it would be useful! 1> Use of non-blocking statements: Use it only within SEQUENTIAL 'always' blocks (eg - if the sensitivity list contains a clock signal). A blocking statement here can cause Verilog race conditions. 2> Use of blocking...
- dpaul81
- Post #9
- Mar 29, 2011
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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[SOLVED] Need suggestions for logic flow

Re: Need suggestions for logic flow - Endianness Conversion 1st of all my apologies for the misconception about Endianness! Thanks 'lostinxlation' for the clarification! So what I essentially need is that, there r two systems interconnected by a bus-system and they have to exchange data. 32...
- dpaul81
- Post #8
- Mar 25, 2011
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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[SOLVED] Need suggestions for logic flow

Hi all, I need to convert data from big-endian to small-endian and vice-versa. So that would essentially be the MSB bit taking the position of LSB bit and the LSB bit goes to the MSB position. The bit in position MSB-1 would take the position LSB+1 and the bit in LSB+1 would take the MSB-1...
- dpaul81
- Thread
- Mar 24, 2011
- Replies: 7
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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[SOLVED] Error in Verilog code

Thanks "j_andr" for pointing out the difference.
- dpaul81
- Post #10
- Mar 23, 2011
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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[SOLVED] Error in Verilog code

ok...then I'll accept it as a rule that output ports that deliver data needs to be declared as an internal variable of type register. I have a Verilog book at hand, but I am running against time (can't read through the basic chapters now)! Need to pick up Verilog as fast as possible and then...
- dpaul81
- Post #6
- Mar 22, 2011
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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[SOLVED] Error in Verilog code

Thanks to all those who have replied! @ above : If I have understood properly, your suggestion means that the output port has to be declared as a register 'cnt_out'. Now why would I do that? Is there any other way to solve the issue? What I really want to do is to work with an internal 8 bit...
- dpaul81
- Post #4
- Mar 22, 2011
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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[SOLVED] Error in Verilog code

HI all, I am very new to Verilog and am getting the following error! "A net is not a legal lvalue in this context" The places where I am getting the errors have been marked in the code given below: `timescale 1 ns / 1 ns module up_down_counter (clk, n_reset, up_down, inp_data, cnt_out); //...
- dpaul81
- Thread
- Mar 22, 2011
- Replies: 9
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design

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dpaul81

Welcome to EDAboard.com

Recent content by dpaul81

Look up table for sine wave generation

Look up table for sine wave generation

[SOLVED] OpenSource Tool for creating Timing Diagrams

[SOLVED] OpenSource Tool for creating Timing Diagrams

Use of 'inout' ports in Verilog

Use of 'inout' ports in Verilog

blocking and non-blocking statements in verilog?

[SOLVED] Need suggestions for logic flow

[SOLVED] Need suggestions for logic flow

[SOLVED] Error in Verilog code

[SOLVED] Error in Verilog code

[SOLVED] Error in Verilog code

[SOLVED] Error in Verilog code

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